Commit 3dff4c62 authored by David S. Miller's avatar David S. Miller

Merge branch 'hns3-new-features'

Peng Li says:

====================
add some features to hns3 driver

This patchset adds some features to hns3 driver, include the support
for ethtool command -d, -p and support for manager table.

[Patch 1/4] adds support for ethtool command -d, its ops is get_regs.
driver will send command to command queue, and get regs number and
regs value from command queue.
[Patch 2/4] adds manager table initialization for hardware.
[Patch 3/4] adds support for ethtool command -p. For fiber ports, driver
sends command to command queue, and IMP will write SGPIO regs to control
leds.
[Patch 4/4] adds support for net status led for fiber ports. Net status
include  port speed, total rx/tx packets and link status. Driver send
the status to command queue, and IMP will write SGPIO to control leds.

---
Change log:
V1 -> V2:
1, fix comments from Andrew Lunn, remove the patch "net: hns3: add
ethtool -p support for phy device".
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b2d3bcfa 716aaac1
...@@ -356,7 +356,8 @@ struct hnae3_ae_ops { ...@@ -356,7 +356,8 @@ struct hnae3_ae_ops {
u32 stringset, u8 *data); u32 stringset, u8 *data);
int (*get_sset_count)(struct hnae3_handle *handle, int stringset); int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
void (*get_regs)(struct hnae3_handle *handle, void *data); void (*get_regs)(struct hnae3_handle *handle, u32 *version,
void *data);
int (*get_regs_len)(struct hnae3_handle *handle); int (*get_regs_len)(struct hnae3_handle *handle);
u32 (*get_rss_key_size)(struct hnae3_handle *handle); u32 (*get_rss_key_size)(struct hnae3_handle *handle);
...@@ -404,6 +405,8 @@ struct hnae3_ae_ops { ...@@ -404,6 +405,8 @@ struct hnae3_ae_ops {
int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num); int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num);
void (*get_flowctrl_adv)(struct hnae3_handle *handle, void (*get_flowctrl_adv)(struct hnae3_handle *handle,
u32 *flowctrl_adv); u32 *flowctrl_adv);
int (*set_led_id)(struct hnae3_handle *handle,
enum ethtool_phys_id_state status);
}; };
struct hnae3_dcb_ops { struct hnae3_dcb_ops {
......
...@@ -1063,6 +1063,38 @@ static int hns3_set_coalesce(struct net_device *netdev, ...@@ -1063,6 +1063,38 @@ static int hns3_set_coalesce(struct net_device *netdev,
return 0; return 0;
} }
static int hns3_get_regs_len(struct net_device *netdev)
{
struct hnae3_handle *h = hns3_get_handle(netdev);
if (!h->ae_algo->ops->get_regs_len)
return -EOPNOTSUPP;
return h->ae_algo->ops->get_regs_len(h);
}
static void hns3_get_regs(struct net_device *netdev,
struct ethtool_regs *cmd, void *data)
{
struct hnae3_handle *h = hns3_get_handle(netdev);
if (!h->ae_algo->ops->get_regs)
return;
h->ae_algo->ops->get_regs(h, &cmd->version, data);
}
static int hns3_set_phys_id(struct net_device *netdev,
enum ethtool_phys_id_state state)
{
struct hnae3_handle *h = hns3_get_handle(netdev);
if (!h->ae_algo || !h->ae_algo->ops || !h->ae_algo->ops->set_led_id)
return -EOPNOTSUPP;
return h->ae_algo->ops->set_led_id(h, state);
}
static const struct ethtool_ops hns3vf_ethtool_ops = { static const struct ethtool_ops hns3vf_ethtool_ops = {
.get_drvinfo = hns3_get_drvinfo, .get_drvinfo = hns3_get_drvinfo,
.get_ringparam = hns3_get_ringparam, .get_ringparam = hns3_get_ringparam,
...@@ -1103,6 +1135,9 @@ static const struct ethtool_ops hns3_ethtool_ops = { ...@@ -1103,6 +1135,9 @@ static const struct ethtool_ops hns3_ethtool_ops = {
.set_channels = hns3_set_channels, .set_channels = hns3_set_channels,
.get_coalesce = hns3_get_coalesce, .get_coalesce = hns3_get_coalesce,
.set_coalesce = hns3_set_coalesce, .set_coalesce = hns3_set_coalesce,
.get_regs_len = hns3_get_regs_len,
.get_regs = hns3_get_regs,
.set_phys_id = hns3_set_phys_id,
}; };
void hns3_ethtool_set_ops(struct net_device *netdev) void hns3_ethtool_set_ops(struct net_device *netdev)
......
...@@ -102,6 +102,10 @@ enum hclge_opcode_type { ...@@ -102,6 +102,10 @@ enum hclge_opcode_type {
HCLGE_OPC_STATS_64_BIT = 0x0030, HCLGE_OPC_STATS_64_BIT = 0x0030,
HCLGE_OPC_STATS_32_BIT = 0x0031, HCLGE_OPC_STATS_32_BIT = 0x0031,
HCLGE_OPC_STATS_MAC = 0x0032, HCLGE_OPC_STATS_MAC = 0x0032,
HCLGE_OPC_QUERY_REG_NUM = 0x0040,
HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
/* Device management command */ /* Device management command */
/* MAC commond */ /* MAC commond */
...@@ -111,6 +115,7 @@ enum hclge_opcode_type { ...@@ -111,6 +115,7 @@ enum hclge_opcode_type {
HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
HCLGE_OPC_STATS_MAC_TRAFFIC = 0x0314,
/* MACSEC command */ /* MACSEC command */
/* PFC/Pause CMD*/ /* PFC/Pause CMD*/
...@@ -223,6 +228,9 @@ enum hclge_opcode_type { ...@@ -223,6 +228,9 @@ enum hclge_opcode_type {
/* Mailbox cmd */ /* Mailbox cmd */
HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
/* Led command */
HCLGE_OPC_LED_STATUS_CFG = 0xB000,
}; };
#define HCLGE_TQP_REG_OFFSET 0x80000 #define HCLGE_TQP_REG_OFFSET 0x80000
...@@ -601,6 +609,28 @@ struct hclge_mac_vlan_mask_entry_cmd { ...@@ -601,6 +609,28 @@ struct hclge_mac_vlan_mask_entry_cmd {
u8 rsv2[14]; u8 rsv2[14];
}; };
#define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
#define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
#define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
#define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc
struct hclge_mac_mgr_tbl_entry_cmd {
u8 flags;
u8 resp_code;
__le16 vlan_tag;
__le32 mac_addr_hi32;
__le16 mac_addr_lo16;
__le16 rsv1;
__le16 ethter_type;
__le16 egress_port;
__le16 egress_queue;
u8 sw_port_id_aware;
u8 rsv2;
u8 i_port_bitmap;
u8 i_port_direction;
u8 rsv3[2];
};
#define HCLGE_CFG_MTA_MAC_SEL_S 0x0 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0
#define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0) #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0)
#define HCLGE_CFG_MTA_MAC_EN_B 0x7 #define HCLGE_CFG_MTA_MAC_EN_B 0x7
...@@ -781,6 +811,23 @@ struct hclge_reset_cmd { ...@@ -781,6 +811,23 @@ struct hclge_reset_cmd {
#define HCLGE_NIC_CMQ_DESC_NUM 1024 #define HCLGE_NIC_CMQ_DESC_NUM 1024
#define HCLGE_NIC_CMQ_DESC_NUM_S 3 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
#define HCLGE_LED_PORT_SPEED_STATE_S 0
#define HCLGE_LED_PORT_SPEED_STATE_M GENMASK(5, 0)
#define HCLGE_LED_ACTIVITY_STATE_S 0
#define HCLGE_LED_ACTIVITY_STATE_M GENMASK(1, 0)
#define HCLGE_LED_LINK_STATE_S 0
#define HCLGE_LED_LINK_STATE_M GENMASK(1, 0)
#define HCLGE_LED_LOCATE_STATE_S 0
#define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
struct hclge_set_led_state_cmd {
u8 port_speed_led_config;
u8 link_led_config;
u8 activity_led_config;
u8 locate_led_config;
u8 rsv[20];
};
int hclge_cmd_init(struct hclge_dev *hdev); int hclge_cmd_init(struct hclge_dev *hdev);
static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
{ {
......
...@@ -550,6 +550,9 @@ struct hclge_dev { ...@@ -550,6 +550,9 @@ struct hclge_dev {
bool accept_mta_mc; /* Whether accept mta filter multicast */ bool accept_mta_mc; /* Whether accept mta filter multicast */
struct hclge_vlan_type_cfg vlan_type_cfg; struct hclge_vlan_type_cfg vlan_type_cfg;
u64 rx_pkts_for_led;
u64 tx_pkts_for_led;
}; };
/* VPort level vlan tag configuration for TX direction */ /* VPort level vlan tag configuration for TX direction */
......
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