Commit 40ce1121 authored by Jocelyn Falempe's avatar Jocelyn Falempe Committed by Thomas Zimmermann

drm/mgag200: Fix PLL setup for g200wb and g200ew

commit f86c3ed5 ("drm/mgag200: Split PLL setup into compute and
 update functions") introduced a regression for g200wb and g200ew.
The PLLs are not set up properly, and VGA screen stays
black, or displays "out of range" message.

MGA1064_WB_PIX_PLLC_N/M/P was mistakenly replaced with
MGA1064_PIX_PLLC_N/M/P which have different addresses.

Patch tested on a Dell T310 with g200wb

Fixes: f86c3ed5 ("drm/mgag200: Split PLL setup into compute and update functions")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJocelyn Falempe <jfalempe@redhat.com>
Signed-off-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220308174321.225606-1-jfalempe@redhat.com
parent 9470c29f
......@@ -404,9 +404,9 @@ mgag200_pixpll_update_g200wb(struct mgag200_pll *pixpll, const struct mgag200_pl
udelay(50);
/* program pixel pll register */
WREG_DAC(MGA1064_PIX_PLLC_N, xpixpllcn);
WREG_DAC(MGA1064_PIX_PLLC_M, xpixpllcm);
WREG_DAC(MGA1064_PIX_PLLC_P, xpixpllcp);
WREG_DAC(MGA1064_WB_PIX_PLLC_N, xpixpllcn);
WREG_DAC(MGA1064_WB_PIX_PLLC_M, xpixpllcm);
WREG_DAC(MGA1064_WB_PIX_PLLC_P, xpixpllcp);
udelay(50);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment