Commit 40d957e6 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi

PCI: cadence: Add support to start link and verify link status

Add cdns_pcie_ops to start link and verify link status. The registers
to start link and to check link status is in Platform specific PCIe
wrapper. Add support for platform specific drivers to add callback
functions for the PCIe Cadence core to start link and verify link status.

Link: https://lore.kernel.org/r/20200722110317.4744-6-kishon@ti.comSigned-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent a8b661eb
...@@ -357,8 +357,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) ...@@ -357,8 +357,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
{ {
struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie; struct cdns_pcie *pcie = &ep->pcie;
struct device *dev = pcie->dev;
struct pci_epf *epf; struct pci_epf *epf;
u32 cfg; u32 cfg;
int ret;
/* /*
* BIT(0) is hardwired to 1, hence function 0 is always enabled * BIT(0) is hardwired to 1, hence function 0 is always enabled
...@@ -369,6 +371,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) ...@@ -369,6 +371,12 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
cfg |= BIT(epf->func_no); cfg |= BIT(epf->func_no);
cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
ret = cdns_pcie_start_link(pcie);
if (ret) {
dev_err(dev, "Failed to start link\n");
return ret;
}
return 0; return 0;
} }
......
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
// Cadence PCIe host controller driver. // Cadence PCIe host controller driver.
// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com> // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
#include <linux/delay.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/list_sort.h> #include <linux/list_sort.h>
#include <linux/of_address.h> #include <linux/of_address.h>
...@@ -420,6 +421,23 @@ static int cdns_pcie_host_init(struct device *dev, ...@@ -420,6 +421,23 @@ static int cdns_pcie_host_init(struct device *dev,
return err; return err;
} }
static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
{
struct device *dev = pcie->dev;
int retries;
/* Check if the link is up or not */
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
if (cdns_pcie_link_up(pcie)) {
dev_info(dev, "Link up\n");
return 0;
}
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
}
return -ETIMEDOUT;
}
int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
{ {
struct device *dev = rc->pcie.dev; struct device *dev = rc->pcie.dev;
...@@ -468,6 +486,16 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ...@@ -468,6 +486,16 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
pcie->mem_res = res; pcie->mem_res = res;
ret = cdns_pcie_start_link(pcie);
if (ret) {
dev_err(dev, "Failed to start link\n");
return ret;
}
ret = cdns_pcie_host_wait_for_link(pcie);
if (ret)
dev_dbg(dev, "PCIe link never came up\n");
for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
rc->avail_ib_bar[bar] = true; rc->avail_ib_bar[bar] = true;
......
...@@ -10,6 +10,11 @@ ...@@ -10,6 +10,11 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/phy/phy.h> #include <linux/phy/phy.h>
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
/* /*
* Local Management Registers * Local Management Registers
*/ */
...@@ -245,12 +250,20 @@ enum cdns_pcie_msg_routing { ...@@ -245,12 +250,20 @@ enum cdns_pcie_msg_routing {
MSG_ROUTING_GATHER, MSG_ROUTING_GATHER,
}; };
struct cdns_pcie_ops {
int (*start_link)(struct cdns_pcie *pcie);
void (*stop_link)(struct cdns_pcie *pcie);
bool (*link_up)(struct cdns_pcie *pcie);
};
/** /**
* struct cdns_pcie - private data for Cadence PCIe controller drivers * struct cdns_pcie - private data for Cadence PCIe controller drivers
* @reg_base: IO mapped register base * @reg_base: IO mapped register base
* @mem_res: start/end offsets in the physical system memory to map PCI accesses * @mem_res: start/end offsets in the physical system memory to map PCI accesses
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
* @bus: In Root Complex mode, the bus number * @bus: In Root Complex mode, the bus number
* @ops: Platform specific ops to control various inputs from Cadence PCIe
* wrapper
*/ */
struct cdns_pcie { struct cdns_pcie {
void __iomem *reg_base; void __iomem *reg_base;
...@@ -261,7 +274,7 @@ struct cdns_pcie { ...@@ -261,7 +274,7 @@ struct cdns_pcie {
int phy_count; int phy_count;
struct phy **phy; struct phy **phy;
struct device_link **link; struct device_link **link;
const struct cdns_pcie_common_ops *ops; const struct cdns_pcie_ops *ops;
}; };
/** /**
...@@ -426,6 +439,28 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) ...@@ -426,6 +439,28 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
} }
static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
{
if (pcie->ops->start_link)
return pcie->ops->start_link(pcie);
return 0;
}
static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
{
if (pcie->ops->stop_link)
pcie->ops->stop_link(pcie);
}
static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
{
if (pcie->ops->link_up)
return pcie->ops->link_up(pcie);
return true;
}
#ifdef CONFIG_PCIE_CADENCE_HOST #ifdef CONFIG_PCIE_CADENCE_HOST
int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
#else #else
......
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