Blackfin: SMP: fix cpudata cache setup

After some cache setup reordering changesets, the blackfin_cpudata init
was left behind.  While cpu0's data was correct, cpu1's data was not.
Not that big of a deal as these are only used in the cpuinfo output, but
should still be fixed.  So move the setup of these fields to the common
cache setup function to avoid this happening again in the future.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

arch/blackfin/kernel/setup.c

@@ -105,6 +105,8 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
 	bfin_dcache_init(dcplb_tbl[cpu]);
 #endif
 
+	bfin_setup_cpudata(cpu);
+
 	/*
 	 * In cache coherence emulation mode, we need to have the
 	 * D-cache enabled before running any atomic operation which
@@ -1036,8 +1038,6 @@ void __init setup_arch(char **cmdline_p)
 static int __init topology_init(void)
 {
 	unsigned int cpu;
-	/* Record CPU-private information for the boot processor. */
-	bfin_setup_cpudata(0);
 
 	for_each_possible_cpu(cpu) {
 		register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);

arch/blackfin/mach-bf561/smp.c

@@ -62,9 +62,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
 	SSYNC();
 
-	/* Store CPU-private information to the cpu_data array. */
-	bfin_setup_cpudata(cpu);
-
 	/* We are done with local CPU inits, unblock the boot CPU. */
 	set_cpu_online(cpu, true);
 	spin_lock(&boot_lock);