Commit 447976ab authored by Jianlong Huang's avatar Jianlong Huang Committed by Linus Walleij

pinctrl: starfive: Add StarFive JH7110 sys controller driver

Add pinctrl driver for StarFive JH7110 SoC sys pinctrl controller.
Co-developed-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Signed-off-by: default avatarJianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: default avatarHal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230209143702.44408-4-hal.feng@starfivetech.comSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 716129d3
......@@ -19896,7 +19896,7 @@ M: Jianlong Huang <jianlong.huang@starfivetech.com>
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
F: drivers/pinctrl/starfive/
F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
......
......@@ -16,3 +16,24 @@ config PINCTRL_STARFIVE_JH7100
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
config PINCTRL_STARFIVE_JH7110
bool
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
config PINCTRL_STARFIVE_JH7110_SYS
tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
depends on SOC_STARFIVE || COMPILE_TEST
depends on OF
select PINCTRL_STARFIVE_JH7110
default SOC_STARFIVE
help
Say yes here to support system pin control on the StarFive JH7110 SoC.
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Pinctrl / GPIO driver for StarFive JH7110 SoC
*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __PINCTRL_STARFIVE_JH7110_H__
#define __PINCTRL_STARFIVE_JH7110_H__
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
struct jh7110_pinctrl {
struct device *dev;
struct gpio_chip gc;
struct pinctrl_gpio_range gpios;
raw_spinlock_t lock;
void __iomem *base;
struct pinctrl_dev *pctl;
/* register read/write mutex */
struct mutex mutex;
const struct jh7110_pinctrl_soc_info *info;
};
struct jh7110_gpio_irq_reg {
unsigned int is_reg_base;
unsigned int ic_reg_base;
unsigned int ibe_reg_base;
unsigned int iev_reg_base;
unsigned int ie_reg_base;
unsigned int ris_reg_base;
unsigned int mis_reg_base;
};
struct jh7110_pinctrl_soc_info {
const struct pinctrl_pin_desc *pins;
unsigned int npins;
unsigned int ngpios;
unsigned int gc_base;
/* gpio dout/doen/din/gpioinput register */
unsigned int dout_reg_base;
unsigned int dout_mask;
unsigned int doen_reg_base;
unsigned int doen_mask;
unsigned int gpi_reg_base;
unsigned int gpi_mask;
unsigned int gpioin_reg_base;
const struct jh7110_gpio_irq_reg *irq_reg;
/* generic pinmux */
int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp,
unsigned int pin,
unsigned int din, u32 dout,
u32 doen, u32 func);
/* gpio chip */
int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp,
unsigned int pin);
void (*jh7110_gpio_irq_handler)(struct irq_desc *desc);
int (*jh7110_gpio_init_hw)(struct gpio_chip *gc);
};
void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
unsigned int din, u32 dout, u32 doen);
int jh7110_pinctrl_probe(struct platform_device *pdev);
struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc);
#endif /* __PINCTRL_STARFIVE_JH7110_H__ */
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