Commit 474adce4 authored by Dorcas AnonoLitunya's avatar Dorcas AnonoLitunya Committed by Greg Kroah-Hartman

Staging: sm750fb: Rename pModeParam

Rename variable pModeParam to mode_param. This follows snakecase naming
convention and ensures a consistent naming style throughout the file.
Issue found by checkpatch.

Mutes the following checkpatch error:
CHECK: Avoid CamelCase: <pModeParam>
Signed-off-by: default avatarDorcas AnonoLitunya <anonolitunya@gmail.com>
Link: https://lore.kernel.org/r/20231016201434.7880-3-anonolitunya@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent fd79614e
...@@ -14,13 +14,13 @@ ...@@ -14,13 +14,13 @@
* in bit 29:27 of Display Control register. * in bit 29:27 of Display Control register.
*/ */
static unsigned long static unsigned long
display_control_adjust_SM750LE(struct mode_parameter *pModeParam, display_control_adjust_SM750LE(struct mode_parameter *mode_param,
unsigned long dispControl) unsigned long dispControl)
{ {
unsigned long x, y; unsigned long x, y;
x = pModeParam->horizontal_display_end; x = mode_param->horizontal_display_end;
y = pModeParam->vertical_display_end; y = mode_param->vertical_display_end;
/* /*
* SM750LE has to set up the top-left and bottom-right * SM750LE has to set up the top-left and bottom-right
...@@ -75,7 +75,7 @@ display_control_adjust_SM750LE(struct mode_parameter *pModeParam, ...@@ -75,7 +75,7 @@ display_control_adjust_SM750LE(struct mode_parameter *pModeParam,
} }
/* only timing related registers will be programed */ /* only timing related registers will be programed */
static int programModeRegisters(struct mode_parameter *pModeParam, static int programModeRegisters(struct mode_parameter *mode_param,
struct pll_value *pll) struct pll_value *pll)
{ {
int ret = 0; int ret = 0;
...@@ -86,46 +86,46 @@ static int programModeRegisters(struct mode_parameter *pModeParam, ...@@ -86,46 +86,46 @@ static int programModeRegisters(struct mode_parameter *pModeParam,
/* programe secondary pixel clock */ /* programe secondary pixel clock */
poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
tmp = ((pModeParam->horizontal_total - 1) << tmp = ((mode_param->horizontal_total - 1) <<
CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) & CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
CRT_HORIZONTAL_TOTAL_TOTAL_MASK; CRT_HORIZONTAL_TOTAL_TOTAL_MASK;
tmp |= (pModeParam->horizontal_display_end - 1) & tmp |= (mode_param->horizontal_display_end - 1) &
CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK; CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK;
poke32(CRT_HORIZONTAL_TOTAL, tmp); poke32(CRT_HORIZONTAL_TOTAL, tmp);
tmp = (pModeParam->horizontal_sync_width << tmp = (mode_param->horizontal_sync_width <<
CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) & CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) &
CRT_HORIZONTAL_SYNC_WIDTH_MASK; CRT_HORIZONTAL_SYNC_WIDTH_MASK;
tmp |= (pModeParam->horizontal_sync_start - 1) & tmp |= (mode_param->horizontal_sync_start - 1) &
CRT_HORIZONTAL_SYNC_START_MASK; CRT_HORIZONTAL_SYNC_START_MASK;
poke32(CRT_HORIZONTAL_SYNC, tmp); poke32(CRT_HORIZONTAL_SYNC, tmp);
tmp = ((pModeParam->vertical_total - 1) << tmp = ((mode_param->vertical_total - 1) <<
CRT_VERTICAL_TOTAL_TOTAL_SHIFT) & CRT_VERTICAL_TOTAL_TOTAL_SHIFT) &
CRT_VERTICAL_TOTAL_TOTAL_MASK; CRT_VERTICAL_TOTAL_TOTAL_MASK;
tmp |= (pModeParam->vertical_display_end - 1) & tmp |= (mode_param->vertical_display_end - 1) &
CRT_VERTICAL_TOTAL_DISPLAY_END_MASK; CRT_VERTICAL_TOTAL_DISPLAY_END_MASK;
poke32(CRT_VERTICAL_TOTAL, tmp); poke32(CRT_VERTICAL_TOTAL, tmp);
tmp = ((pModeParam->vertical_sync_height << tmp = ((mode_param->vertical_sync_height <<
CRT_VERTICAL_SYNC_HEIGHT_SHIFT)) & CRT_VERTICAL_SYNC_HEIGHT_SHIFT)) &
CRT_VERTICAL_SYNC_HEIGHT_MASK; CRT_VERTICAL_SYNC_HEIGHT_MASK;
tmp |= (pModeParam->vertical_sync_start - 1) & tmp |= (mode_param->vertical_sync_start - 1) &
CRT_VERTICAL_SYNC_START_MASK; CRT_VERTICAL_SYNC_START_MASK;
poke32(CRT_VERTICAL_SYNC, tmp); poke32(CRT_VERTICAL_SYNC, tmp);
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity) if (mode_param->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE; tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity) if (mode_param->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE; tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (sm750_get_chip_type() == SM750LE) { if (sm750_get_chip_type() == SM750LE) {
display_control_adjust_SM750LE(pModeParam, tmp); display_control_adjust_SM750LE(mode_param, tmp);
} else { } else {
reg = peek32(CRT_DISPLAY_CTRL) & reg = peek32(CRT_DISPLAY_CTRL) &
~(DISPLAY_CTRL_VSYNC_PHASE | ~(DISPLAY_CTRL_VSYNC_PHASE |
...@@ -140,40 +140,40 @@ static int programModeRegisters(struct mode_parameter *pModeParam, ...@@ -140,40 +140,40 @@ static int programModeRegisters(struct mode_parameter *pModeParam,
poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
reg = ((pModeParam->horizontal_total - 1) << reg = ((mode_param->horizontal_total - 1) <<
PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) & PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
PANEL_HORIZONTAL_TOTAL_TOTAL_MASK; PANEL_HORIZONTAL_TOTAL_TOTAL_MASK;
reg |= ((pModeParam->horizontal_display_end - 1) & reg |= ((mode_param->horizontal_display_end - 1) &
PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK); PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK);
poke32(PANEL_HORIZONTAL_TOTAL, reg); poke32(PANEL_HORIZONTAL_TOTAL, reg);
poke32(PANEL_HORIZONTAL_SYNC, poke32(PANEL_HORIZONTAL_SYNC,
((pModeParam->horizontal_sync_width << ((mode_param->horizontal_sync_width <<
PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) & PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) &
PANEL_HORIZONTAL_SYNC_WIDTH_MASK) | PANEL_HORIZONTAL_SYNC_WIDTH_MASK) |
((pModeParam->horizontal_sync_start - 1) & ((mode_param->horizontal_sync_start - 1) &
PANEL_HORIZONTAL_SYNC_START_MASK)); PANEL_HORIZONTAL_SYNC_START_MASK));
poke32(PANEL_VERTICAL_TOTAL, poke32(PANEL_VERTICAL_TOTAL,
(((pModeParam->vertical_total - 1) << (((mode_param->vertical_total - 1) <<
PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) & PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) &
PANEL_VERTICAL_TOTAL_TOTAL_MASK) | PANEL_VERTICAL_TOTAL_TOTAL_MASK) |
((pModeParam->vertical_display_end - 1) & ((mode_param->vertical_display_end - 1) &
PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK)); PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK));
poke32(PANEL_VERTICAL_SYNC, poke32(PANEL_VERTICAL_SYNC,
((pModeParam->vertical_sync_height << ((mode_param->vertical_sync_height <<
PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) & PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) &
PANEL_VERTICAL_SYNC_HEIGHT_MASK) | PANEL_VERTICAL_SYNC_HEIGHT_MASK) |
((pModeParam->vertical_sync_start - 1) & ((mode_param->vertical_sync_start - 1) &
PANEL_VERTICAL_SYNC_START_MASK)); PANEL_VERTICAL_SYNC_START_MASK));
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE; tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity) if (mode_param->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE; tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity) if (mode_param->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE; tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (pModeParam->clock_phase_polarity) if (mode_param->clock_phase_polarity)
tmp |= DISPLAY_CTRL_CLOCK_PHASE; tmp |= DISPLAY_CTRL_CLOCK_PHASE;
reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK | reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
......
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