Commit 48066267 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  MIPS: Fix CONFIG_FLATMEM version of pfn_valid()
  MIPS: Reorganize Cavium OCTEON PCI support.
  Update Yoichi Yuasa's e-mail address
  MIPS: Allow suspend and hibernation again on uniprocessor kernels.
  MIPS: 64-bit: Fix o32 core dump
  MIPS: BC47xx: Fix SSB irq setup
  MIPS: CMP: Update sync-r4k for current kernel
  MIPS: CMP: Move gcmp_probe to before the SMP ops
  MIPS: CMP: activate CMP support
  MIPS: CMP: Extend IPI handling to CPU number
  MIPS: CMP: Extend the GIC IPI interrupts beyond 32
  MIPS: Define __arch_swab64 for all mips r2 cpus
  MIPS: Update VR41xx GPIO driver to use gpiolib
  MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open.
  MIPS: Malta: Remove unnecessary function prototypes
  MIPS: MT: Remove unnecessary semicolons
  MIPS: Add support for Texas Instruments AR7 System-on-a-Chip
parents f1a74571 baf92278
......@@ -22,6 +22,26 @@ choice
config MACH_ALCHEMY
bool "Alchemy processor based machines"
config AR7
bool "Texas Instruments AR7"
select BOOT_ELF32
select DMA_NONCOHERENT
select CEVT_R4K
select CSRC_R4K
select IRQ_CPU
select NO_EXCEPT_FILL
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_GPIO
select GCD
select VLYNQ
help
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
......@@ -209,7 +229,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS_CMP if BROKEN # because SYNC_R4K is broken
select SYS_SUPPORTS_MIPS_CMP
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_SMARTMIPS
help
......@@ -247,6 +267,7 @@ config MACH_VR41XX
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select ARCH_REQUIRE_GPIOLIB
config NXP_STB220
bool "NXP STB220 board"
......@@ -1635,7 +1656,7 @@ config MIPS_APSP_KSPD
config MIPS_CMP
bool "MIPS CMP framework support"
depends on SYS_SUPPORTS_MIPS_CMP
select SYNC_R4K if BROKEN
select SYNC_R4K
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_SCHED_SMT if SMP
select WEAK_ORDERING
......@@ -2147,11 +2168,11 @@ menu "Power management options"
config ARCH_HIBERNATION_POSSIBLE
def_bool y
depends on SYS_SUPPORTS_HOTPLUG_CPU
depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on SYS_SUPPORTS_HOTPLUG_CPU
depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
source "kernel/power/Kconfig"
......
......@@ -172,6 +172,13 @@ libs-y += arch/mips/fw/lib/
# Board-dependent options and extra files
#
#
# Texas Instruments AR7
#
core-$(CONFIG_AR7) += arch/mips/ar7/
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
load-$(CONFIG_AR7) += 0xffffffff94100000
#
# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
#
......
obj-y := \
prom.o \
setup.o \
memory.o \
irq.o \
time.o \
platform.o \
gpio.o \
clock.o
This diff is collapsed.
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <asm/mach-ar7/gpio.h>
static const char *ar7_gpio_list[AR7_GPIO_MAX];
int gpio_request(unsigned gpio, const char *label)
{
if (gpio >= AR7_GPIO_MAX)
return -EINVAL;
if (ar7_gpio_list[gpio])
return -EBUSY;
if (label)
ar7_gpio_list[gpio] = label;
else
ar7_gpio_list[gpio] = "busy";
return 0;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned gpio)
{
BUG_ON(!ar7_gpio_list[gpio]);
ar7_gpio_list[gpio] = NULL;
}
EXPORT_SYMBOL(gpio_free);
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-ar7/ar7.h>
#define EXCEPT_OFFSET 0x80
#define PACE_OFFSET 0xA0
#define CHNLS_OFFSET 0x200
#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
#define PIR_OFFSET (0x40)
#define MSR_OFFSET (0x44)
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
static int ar7_irq_base;
static void ar7_unmask_irq(unsigned int irq)
{
writel(1 << ((irq - ar7_irq_base) % 32),
REG(ESR_OFFSET(irq - ar7_irq_base)));
}
static void ar7_mask_irq(unsigned int irq)
{
writel(1 << ((irq - ar7_irq_base) % 32),
REG(ECR_OFFSET(irq - ar7_irq_base)));
}
static void ar7_ack_irq(unsigned int irq)
{
writel(1 << ((irq - ar7_irq_base) % 32),
REG(CR_OFFSET(irq - ar7_irq_base)));
}
static void ar7_unmask_sec_irq(unsigned int irq)
{
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
}
static void ar7_mask_sec_irq(unsigned int irq)
{
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
}
static void ar7_ack_sec_irq(unsigned int irq)
{
writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
}
static struct irq_chip ar7_irq_type = {
.name = "AR7",
.unmask = ar7_unmask_irq,
.mask = ar7_mask_irq,
.ack = ar7_ack_irq
};
static struct irq_chip ar7_sec_irq_type = {
.name = "AR7",
.unmask = ar7_unmask_sec_irq,
.mask = ar7_mask_sec_irq,
.ack = ar7_ack_sec_irq,
};
static struct irqaction ar7_cascade_action = {
.handler = no_action,
.name = "AR7 cascade interrupt"
};
static void __init ar7_irq_init(int base)
{
int i;
/*
* Disable interrupts and clear pending
*/
writel(0xffffffff, REG(ECR_OFFSET(0)));
writel(0xff, REG(ECR_OFFSET(32)));
writel(0xffffffff, REG(SEC_ECR_OFFSET));
writel(0xffffffff, REG(CR_OFFSET(0)));
writel(0xff, REG(CR_OFFSET(32)));
writel(0xffffffff, REG(SEC_CR_OFFSET));
ar7_irq_base = base;
for (i = 0; i < 40; i++) {
writel(i, REG(CHNL_OFFSET(i)));
/* Primary IRQ's */
set_irq_chip_and_handler(base + i, &ar7_irq_type,
handle_level_irq);
/* Secondary IRQ's */
if (i < 32)
set_irq_chip_and_handler(base + i + 40,
&ar7_sec_irq_type,
handle_level_irq);
}
setup_irq(2, &ar7_cascade_action);
setup_irq(ar7_irq_base, &ar7_cascade_action);
set_c0_status(IE_IRQ0);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
ar7_irq_init(8);
}
static void ar7_cascade(void)
{
u32 status;
int i, irq;
/* Primary IRQ's */
irq = readl(REG(PIR_OFFSET)) & 0x3f;
if (irq) {
do_IRQ(ar7_irq_base + irq);
return;
}
/* Secondary IRQ's are cascaded through primary '0' */
writel(1, REG(CR_OFFSET(irq)));
status = readl(REG(SEC_SR_OFFSET));
for (i = 0; i < 32; i++) {
if (status & 1) {
do_IRQ(ar7_irq_base + i + 40);
return;
}
status >>= 1;
}
spurious_interrupt();
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(7);
else if (pending & STATUSF_IP2) /* int0 hardware line */
ar7_cascade();
else
spurious_interrupt();
}
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/bootmem.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pfn.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/swap.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/sections.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mips-boards/prom.h>
static int __init memsize(void)
{
u32 size = (64 << 20);
u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4);
u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
u32 *tmpaddr = addr;
while (tmpaddr > kernel_end) {
*tmpaddr = (u32)tmpaddr;
size >>= 1;
tmpaddr -= size >> 2;
}
do {
tmpaddr += size >> 2;
if (*tmpaddr != (u32)tmpaddr)
break;
size <<= 1;
} while (size < (64 << 20));
writel(tmpaddr, &addr);
return size;
}
void __init prom_meminit(void)
{
unsigned long pages;
pages = memsize() >> PAGE_SHIFT;
add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT,
BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
/* Nothing to free */
}
This diff is collapsed.
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Putting things on the screen/serial line using YAMONs facilities.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/serial_reg.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <asm/bootinfo.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
#define MAX_ENTRY 80
struct env_var {
char *name;
char *value;
};
static struct env_var adam2_env[MAX_ENTRY];
char *prom_getenv(const char *name)
{
int i;
for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
if (!strcmp(name, adam2_env[i].name))
return adam2_env[i].value;
return NULL;
}
EXPORT_SYMBOL(prom_getenv);
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
static void __init ar7_init_cmdline(int argc, char *argv[])
{
char *cp;
int actr;
actr = 1; /* Always ignore argv[0] */
cp = &(arcs_cmdline[0]);
while (actr < argc) {
strcpy(cp, argv[actr]);
cp += strlen(argv[actr]);
*cp++ = ' ';
actr++;
}
if (cp != &(arcs_cmdline[0])) {
/* get rid of trailing space */
--cp;
*cp = '\0';
}
}
struct psbl_rec {
u32 psbl_size;
u32 env_base;
u32 env_size;
u32 ffs_base;
u32 ffs_size;
};
static __initdata char psp_env_version[] = "TIENV0.8";
struct psp_env_chunk {
u8 num;
u8 ctrl;
u16 csum;
u8 len;
char data[11];
} __attribute__ ((packed));
struct psp_var_map_entry {
u8 num;
char *value;
};
static struct psp_var_map_entry psp_var_map[] = {
{ 1, "cpufrequency" },
{ 2, "memsize" },
{ 3, "flashsize" },
{ 4, "modetty0" },
{ 5, "modetty1" },
{ 8, "maca" },
{ 9, "macb" },
{ 28, "sysfrequency" },
{ 38, "mipsfrequency" },
};
/*
Well-known variable (num is looked up in table above for matching variable name)
Example: cpufrequency=211968000
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Name=Value pair in a single chunk
Example: NAME=VALUE
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Name=Value pair in 2 chunks (len is the number of chunks)
Example: bootloaderVersion=1.3.7.15
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Data is padded with 0xFF
*/
#define PSP_ENV_SIZE 4096
static char psp_env_data[PSP_ENV_SIZE] = { 0, };
static char * __init lookup_psp_var_map(u8 num)
{
int i;
for (i = 0; i < sizeof(psp_var_map); i++)
if (psp_var_map[i].num == num)
return psp_var_map[i].value;
return NULL;
}
static void __init add_adam2_var(char *name, char *value)
{
int i;
for (i = 0; i < MAX_ENTRY; i++) {
if (!adam2_env[i].name) {
adam2_env[i].name = name;
adam2_env[i].value = value;
return;
} else if (!strcmp(adam2_env[i].name, name)) {
adam2_env[i].value = value;
return;
}
}
}
static int __init parse_psp_env(void *psp_env_base)
{
int i, n;
char *name, *value;
struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
i = 1;
n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
while (i < n) {
if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
break;
value = chunks[i].data;
if (chunks[i].num) {
name = lookup_psp_var_map(chunks[i].num);
} else {
name = value;
value += strlen(name) + 1;
}
if (name)
add_adam2_var(name, value);
i += chunks[i].len;
}
return 0;
}
static void __init ar7_init_env(struct env_var *env)
{
int i;
struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
if (strcmp(psp_env, psp_env_version) == 0) {
parse_psp_env(psp_env);
} else {
for (i = 0; i < MAX_ENTRY; i++, env++)
if (env->name)
add_adam2_var(env->name, env->value);
}
}
static void __init console_config(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
char console_string[40];
int baud = 0;
char parity = '\0', bits = '\0', flow = '\0';
char *s, *p;
if (strstr(prom_getcmdline(), "console="))
return;
#ifdef CONFIG_KGDB
if (!strstr(prom_getcmdline(), "nokgdb")) {
strcat(prom_getcmdline(), " console=kgdb");
kgdb_enabled = 1;
return;
}
#endif
s = prom_getenv("modetty0");
if (s) {
baud = simple_strtoul(s, &p, 10);
s = p;
if (*s == ',')
s++;
if (*s)
parity = *s++;
if (*s == ',')
s++;
if (*s)
bits = *s++;
if (*s == ',')
s++;
if (*s == 'h')
flow = 'r';
}
if (baud == 0)
baud = 38400;
if (parity != 'n' && parity != 'o' && parity != 'e')
parity = 'n';
if (bits != '7' && bits != '8')
bits = '8';
if (flow == 'r')
sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
parity, bits, flow);
else
sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
bits);
strcat(prom_getcmdline(), console_string);
#endif
}
void __init prom_init(void)
{
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
ar7_init_env((struct env_var *)fw_arg2);
console_config();
}
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
static inline unsigned int serial_in(int offset)
{
return readl((void *)PORT(offset));
}
static inline void serial_out(int offset, int value)
{
writel(value, (void *)PORT(offset));
}
char prom_getchar(void)
{
while (!(serial_in(UART_LSR) & UART_LSR_DR))
;
return serial_in(UART_RX);
}
int prom_putchar(char c)
{
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
;
serial_out(UART_TX, c);
return 1;
}
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/version.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/time.h>
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
static void ar7_machine_restart(char *command)
{
u32 *softres_reg = ioremap(AR7_REGS_RESET +
AR7_RESET_SOFTWARE, 1);
writel(1, softres_reg);
}
static void ar7_machine_halt(void)
{
while (1)
;
}
static void ar7_machine_power_off(void)
{
u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
u32 power_state = readl(power_reg) | (3 << 30);
writel(power_state, power_reg);
ar7_machine_halt();
}
const char *get_system_type(void)
{
u16 chip_id = ar7_chip_id();
switch (chip_id) {
case AR7_CHIP_7300:
return "TI AR7 (TNETD7300)";
case AR7_CHIP_7100:
return "TI AR7 (TNETD7100)";
case AR7_CHIP_7200:
return "TI AR7 (TNETD7200)";
default:
return "TI AR7 (Unknown)";
}
}
static int __init ar7_init_console(void)
{
return 0;
}
console_initcall(ar7_init_console);
/*
* Initializes basic routines and structures pointers, memory size (as
* given by the bios and saves the command line.
*/
void __init plat_mem_setup(void)
{
unsigned long io_base;
_machine_restart = ar7_machine_restart;
_machine_halt = ar7_machine_halt;
pm_power_off = ar7_machine_power_off;
panic_timeout = 3;
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
if (!io_base)
panic("Can't remap IO base!\n");
set_io_port_base(io_base);
prom_meminit();
printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
get_system_type(),
ar7_chip_id(), ar7_chip_rev());
}
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Setting up the clock on the MIPS boards.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <asm/time.h>
#include <asm/mach-ar7/ar7.h>
void __init plat_time_init(void)
{
mips_hpt_frequency = ar7_cpu_freq() / 2;
}
......@@ -14,9 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_PCI) += pci-common.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_PCI_MSI) += msi.o
EXTRA_CFLAGS += -Werror
......@@ -29,7 +29,7 @@
#include <dma-coherence.h>
#ifdef CONFIG_PCI
#include "pci-common.h"
#include <asm/octeon/pci-octeon.h>
#endif
#define BAR2_PCI_ADDRESS 0x8000000000ul
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
#include "pci-common.h"
typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
/**
* Map a PCI device to the appropriate interrupt line
*
* @param dev The Linux PCI device structure for the device to map
* @param slot The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @param pin The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* @return Interrupt number for the device
*/
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (octeon_pcibios_map_irq)
return octeon_pcibios_map_irq(dev, slot, pin);
else
panic("octeon_pcibios_map_irq doesn't point to a "
"pcibios_map_irq() function");
}
/**
* Called to perform platform specific PCI setup
*
* @param dev
* @return
*/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
uint16_t config;
uint32_t dconfig;
int pos;
/*
* Force the Cache line setting to 64 bytes. The standard
* Linux bus scan doesn't seem to set it. Octeon really has
* 128 byte lines, but Intel bridges get really upset if you
* try and set values above 64 bytes. Value is specified in
* 32bit words.
*/
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
/* Set latency timers for all devices */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
/* Enable reporting System errors and parity errors on all devices */
/* Enable parity checking and error reporting */
pci_read_config_word(dev, PCI_COMMAND, &config);
config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
pci_write_config_word(dev, PCI_COMMAND, config);
if (dev->subordinate) {
/* Set latency timers on sub bridges */
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
/* More bridge error detection */
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
}
/* Enable the PCIe normal error reporting */
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pos) {
/* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
/* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_CERE;
/* Non-Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE;
/* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE;
/* Unsupported Request */
config |= PCI_EXP_DEVCTL_URRE;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
}
/* Find the Advanced Error Reporting capability */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
if (pos) {
/* Clear Uncorrectable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
&dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
dconfig);
/* Enable reporting of all uncorrectable errors */
/* Uncorrectable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
/*
* Leave severity at HW default. This only controls if
* errors are reported as uncorrectable or
* correctable, not if the error is reported.
*/
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
/* Clear Correctable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
/* Enable reporting of all correctable errors */
/* Correctable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
/* Advanced Error Capabilities */
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
/* ECRC Generation Enable */
if (config & PCI_ERR_CAP_ECRC_GENC)
config |= PCI_ERR_CAP_ECRC_GENE;
/* ECRC Check Enable */
if (config & PCI_ERR_CAP_ECRC_CHKC)
config |= PCI_ERR_CAP_ECRC_CHKE;
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
/* Report all errors to the root complex */
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
PCI_ERR_ROOT_CMD_COR_EN |
PCI_ERR_ROOT_CMD_NONFATAL_EN |
PCI_ERR_ROOT_CMD_FATAL_EN);
/* Clear the Root status register */
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
}
return 0;
}
/*
* Cobalt buttons platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Registration of Cobalt LCD platform device.
*
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Registration of Cobalt LED platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Registration of Cobalt MTD device.
*
* Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Registration of Cobalt RTC platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Registration of Cobalt UART platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Cobalt time initialization.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
This diff is collapsed.
/*
* Registration of WRPPMC UART platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Amon support
*/
int amon_cpu_avail(int);
void amon_cpu_start(int, unsigned long, unsigned long,
unsigned long, unsigned long);
/*
* DS1287 timer functions.
*
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -316,9 +316,13 @@ extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
#ifndef ELF_CORE_COPY_REGS
#define ELF_CORE_COPY_REGS(elf_regs, regs) \
elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
#endif
#ifndef ELF_CORE_COPY_TASK_REGS
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
#endif
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
dump_task_fpu(tsk, elf_fpregs)
......
......@@ -114,4 +114,6 @@
#define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */
#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
extern int __init gcmp_probe(unsigned long, unsigned long);
#endif /* _ASM_GCMPREGS_H */
......@@ -20,7 +20,11 @@
#define GIC_TRIG_EDGE 1
#define GIC_TRIG_LEVEL 0
#if CONFIG_SMP
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
#else
#define GIC_NUM_INTRS 32
#endif
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))
......@@ -483,5 +487,7 @@ extern void gic_init(unsigned long gic_base_addr,
extern unsigned int gic_get_int(void);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
#endif /* _ASM_GICREGS_H */
/*
* Galileo/Marvell GT641xx IRQ definitions.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AR7_H__
#define __AR7_H__
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <asm/addrspace.h>
#define AR7_SDRAM_BASE 0x14000000
#define AR7_REGS_BASE 0x08610000
#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
#define AR7_RESET_PEREPHERIAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
#define AR7_RESET_BIT_CPMAC_LO 17
#define AR7_RESET_BIT_CPMAC_HI 21
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
/* Interrupts */
#define AR7_IRQ_UART0 15
#define AR7_IRQ_UART1 16
/* Clocks */
#define AR7_AFE_CLOCK 35328000
#define AR7_REF_CLOCK 25000000
#define AR7_XTAL_CLOCK 24000000
struct plat_cpmac_data {
int reset_bit;
int power_bit;
u32 phy_mask;
char dev_addr[6];
};
struct plat_dsl_data {
int reset_bit_dsl;
int reset_bit_sar;
};
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
static inline u16 ar7_chip_id(void)
{
return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
}
static inline u8 ar7_chip_rev(void)
{
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
}
static inline int ar7_cpu_freq(void)
{
return ar7_cpu_clock;
}
static inline int ar7_bus_freq(void)
{
return ar7_bus_clock;
}
static inline int ar7_vbus_freq(void)
{
return ar7_bus_clock / 2;
}
#define ar7_cpmac_freq ar7_vbus_freq
static inline int ar7_dsp_freq(void)
{
return ar7_dsp_clock;
}
static inline int ar7_has_high_cpmac(void)
{
u16 chip_id = ar7_chip_id();
switch (chip_id) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
return 0;
case AR7_CHIP_7300:
return 1;
default:
return -ENXIO;
}
}
#define ar7_has_high_vlynq ar7_has_high_cpmac
#define ar7_has_second_uart ar7_has_high_cpmac
static inline void ar7_device_enable(u32 bit)
{
void *reset_reg =
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
writel(readl(reset_reg) | (1 << bit), reset_reg);
msleep(20);
}
static inline void ar7_device_disable(u32 bit)
{
void *reset_reg =
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
writel(readl(reset_reg) & ~(1 << bit), reset_reg);
msleep(20);
}
static inline void ar7_device_reset(u32 bit)
{
ar7_device_disable(bit);
ar7_device_enable(bit);
}
static inline void ar7_device_on(u32 bit)
{
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
writel(readl(power_reg) | (1 << bit), power_reg);
msleep(20);
}
static inline void ar7_device_off(u32 bit)
{
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
writel(readl(power_reg) & ~(1 << bit), power_reg);
msleep(20);
}
#endif /* __AR7_H__ */
/*
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AR7_GPIO_H__
#define __AR7_GPIO_H__
#include <asm/mach-ar7/ar7.h>
#define AR7_GPIO_MAX 32
extern int gpio_request(unsigned gpio, const char *label);
extern void gpio_free(unsigned gpio);
/* Common GPIO layer */
static inline int gpio_get_value(unsigned gpio)
{
void __iomem *gpio_in =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
return readl(gpio_in) & (1 << gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
void __iomem *gpio_out =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
unsigned tmp;
tmp = readl(gpio_out) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(tmp, gpio_out);
}
static inline int gpio_direction_input(unsigned gpio)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
if (gpio >= AR7_GPIO_MAX)
return -EINVAL;
writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
return 0;
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
if (gpio >= AR7_GPIO_MAX)
return -EINVAL;
gpio_set_value(gpio, value);
writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
return 0;
}
static inline int gpio_to_irq(unsigned gpio)
{
return -EINVAL;
}
static inline int irq_to_gpio(unsigned irq)
{
return -EINVAL;
}
/* Board specific GPIO functions */
static inline int ar7_gpio_enable(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
writel(readl(gpio_en) | (1 << gpio), gpio_en);
return 0;
}
static inline int ar7_gpio_disable(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
return 0;
}
#include <asm-generic/gpio.h>
#endif
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Shamelessly copied from asm-mips/mach-emma2rh/
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_AR7_IRQ_H
#define __ASM_AR7_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>
#endif /* __ASM_AR7_IRQ_H */
/*
* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __PROM_H__
#define __PROM_H__
extern char *prom_getenv(const char *name);
extern void prom_meminit(void);
#endif /* __PROM_H__ */
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_AR7_SPACES_H
#define _ASM_AR7_SPACES_H
/*
* This handles the memory map.
* We handle pages at KSEG0 for kernels with 32 bit address space.
*/
#define PAGE_OFFSET 0x94000000UL
#define PHYS_OFFSET 0x14000000UL
#include <asm/mach-generic/spaces.h>
#endif /* __ASM_AR7_SPACES_H */
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_AR7_WAR_H
#define __ASM_MIPS_MACH_AR7_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_AR7_WAR_H */
......@@ -8,7 +8,7 @@
* Copyright (C) 1997 Cobalt Microserver
* Copyright (C) 1997, 2003 Ralf Baechle
* Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*/
#ifndef _ASM_COBALT_IRQ_H
#define _ASM_COBALT_IRQ_H
......
/*
* Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -3,23 +3,29 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
* Copyright (C) 2005-2009 Cavium Networks
*/
#ifndef __OCTEON_PCI_COMMON_H__
#define __OCTEON_PCI_COMMON_H__
#ifndef __PCI_OCTEON_H__
#define __PCI_OCTEON_H__
#include <linux/pci.h>
/* Some PCI cards require delays when accessing config space. */
#define PCI_CONFIG_SPACE_DELAY 10000
/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
Octeon specific version pointed to by this variable. This function needs to
change for PCI or PCIe based hosts */
extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
/*
* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
* call the Octeon specific version pointed to by this variable. This
* function needs to change for PCI or PCIe based hosts.
*/
extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
u8 slot, u8 pin);
/* The following defines are only used when octeon_dma_bar_type =
OCTEON_DMA_BAR_TYPE_BIG */
/*
* The following defines are used when octeon_dma_bar_type =
* OCTEON_DMA_BAR_TYPE_BIG
*/
#define OCTEON_PCI_BAR1_HOLE_BITS 5
#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
......@@ -30,9 +36,9 @@ enum octeon_dma_bar_type {
OCTEON_DMA_BAR_TYPE_PCIE
};
/**
* This is a variable to tell the DMA mapping system in dma-octeon.c
* how to map PCI DMA addresses.
/*
* This tells the DMA mapping system in dma-octeon.c how to map PCI
* DMA addresses.
*/
extern enum octeon_dma_bar_type octeon_dma_bar_type;
......
......@@ -165,7 +165,14 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
/* avoid <linux/bootmem.h> include hell */ \
extern unsigned long min_low_pfn; \
\
__pfn >= min_low_pfn && __pfn < max_mapnr; \
})
#elif defined(CONFIG_SPARSEMEM)
......
......@@ -69,7 +69,7 @@
#endif
#ifdef CONFIG_64BIT
#if defined(CONFIG_64BIT) && !defined(WANT_COMPAT_REG_H)
#define EF_R0 0
#define EF_R1 1
......
......@@ -38,7 +38,11 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
}
#define __arch_swab32 __arch_swab32
#ifdef CONFIG_CPU_MIPS64_R2
/*
* Having already checked for CONFIG_CPU_MIPSR2, enable the
* optimized version for 64-bit kernel on r2 CPUs.
*/
#ifdef CONFIG_64BIT
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
{
__asm__(
......@@ -50,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
return x;
}
#define __arch_swab64 __arch_swab64
#endif /* CONFIG_CPU_MIPS64_R2 */
#endif /* CONFIG_64BIT */
#endif /* CONFIG_CPU_MIPSR2 */
#endif /* _ASM_SWAB_H */
......@@ -352,16 +352,18 @@
#define __NR_inotify_init1 (__NR_Linux + 329)
#define __NR_preadv (__NR_Linux + 330)
#define __NR_pwritev (__NR_Linux + 331)
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
#define __NR_perf_counter_open (__NR_Linux + 333)
/*
* Offset of the last Linux o32 flavoured syscall
*/
#define __NR_Linux_syscalls 331
#define __NR_Linux_syscalls 333
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define __NR_O32_Linux 4000
#define __NR_O32_Linux_syscalls 331
#define __NR_O32_Linux_syscalls 333
#if _MIPS_SIM == _MIPS_SIM_ABI64
......@@ -660,16 +662,18 @@
#define __NR_inotify_init1 (__NR_Linux + 288)
#define __NR_preadv (__NR_Linux + 289)
#define __NR_pwritev (__NR_Linux + 290)
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291)
#define __NR_perf_counter_open (__NR_Linux + 292)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
#define __NR_Linux_syscalls 290
#define __NR_Linux_syscalls 292
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000
#define __NR_64_Linux_syscalls 290
#define __NR_64_Linux_syscalls 292
#if _MIPS_SIM == _MIPS_SIM_NABI32
......@@ -972,16 +976,18 @@
#define __NR_inotify_init1 (__NR_Linux + 292)
#define __NR_preadv (__NR_Linux + 293)
#define __NR_pwritev (__NR_Linux + 294)
#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295)
#define __NR_perf_counter_open (__NR_Linux + 296)
/*
* Offset of the last N32 flavoured syscall
*/
#define __NR_Linux_syscalls 294
#define __NR_Linux_syscalls 296
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000
#define __NR_N32_Linux_syscalls 294
#define __NR_N32_Linux_syscalls 296
#ifdef __KERNEL__
......
/*
* capcella.h, Include file for ZAO Networks Capcella.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Include file for NEC VR4100 series General-purpose I/O Unit.
*
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2005-2009 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -41,7 +41,8 @@ typedef enum {
IRQ_SIGNAL_HOLD,
} irq_signal_t;
extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
irq_signal_t signal);
typedef enum {
IRQ_LEVEL_LOW,
......@@ -50,23 +51,6 @@ typedef enum {
extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
typedef enum {
GPIO_DATA_LOW,
GPIO_DATA_HIGH,
GPIO_DATA_INVAL,
} gpio_data_t;
extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
typedef enum {
GPIO_INPUT,
GPIO_OUTPUT,
GPIO_OUTPUT_DISABLE,
} gpio_direction_t;
extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
typedef enum {
GPIO_PULL_DOWN,
GPIO_PULL_UP,
......
......@@ -7,7 +7,7 @@
* Copyright (C) 2001, 2002 Paul Mundt
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2002 TimeSys Corp.
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......
/*
* mpc30x.h, Include file for Victor MP-C303/304.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Include file for NEC VR4100 series PCI Control Unit.
*
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Include file for NEC VR4100 series Serial Interface Unit.
*
* Copyright (C) 2005-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2005-2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* tb0219.h, Include file for TANBAC TB0219.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* Modified for TANBAC TB0219:
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
......
/*
* tb0226.h, Include file for TANBAC TB0226.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -7,7 +7,7 @@
* Copyright (C) 2001, 2002 Paul Mundt
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2002 TimeSys Corp.
* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......
......@@ -53,6 +53,23 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2)
#include <asm/processor.h>
/*
* When this file is selected, we are definitely running a 64bit kernel.
* So using the right regs define in asm/reg.h
*/
#define WANT_COMPAT_REG_H
/* These MUST be defined before elf.h gets included */
extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs);
#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \
({ \
int __res = 1; \
elf32_core_copy_regs(*(_dest), task_pt_regs(_tsk)); \
__res; \
})
#include <linux/module.h>
#include <linux/elfcore.h>
#include <linux/compat.h>
......@@ -110,9 +127,6 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
value->tv_usec = rem / NSEC_PER_USEC;
}
#undef ELF_CORE_COPY_REGS
#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
{
int i;
......
/*
* DS1287 clockevent driver
*
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* GT641xx clockevent routines.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* DEC I/O ASIC's counter clocksource
*
* Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -107,9 +107,7 @@ static unsigned int gic_irq_startup(unsigned int irq)
{
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
irq -= _irqbase;
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
1 << (irq % 32));
GIC_SET_INTR_MASK(irq, 1);
return 0;
}
......@@ -120,8 +118,7 @@ static void gic_irq_ack(unsigned int irq)
#endif
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
irq -= _irqbase;
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
1 << (irq % 32));
GIC_CLR_INTR_MASK(irq, 1);
if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
if (!gic_wedgeb2bok)
......@@ -138,18 +135,14 @@ static void gic_mask_irq(unsigned int irq)
{
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
irq -= _irqbase;
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
1 << (irq % 32));
GIC_CLR_INTR_MASK(irq, 1);
}
static void gic_unmask_irq(unsigned int irq)
{
pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
irq -= _irqbase;
/* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */
GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
1 << (irq % 32));
GIC_SET_INTR_MASK(irq, 1);
}
#ifdef CONFIG_SMP
......@@ -254,6 +247,10 @@ static void __init gic_basic_init(void)
if (cpu == X)
continue;
if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
_intrmap[i].ipiflag == 0)
continue;
setup_intr(_intrmap[i].intrnum,
_intrmap[i].cpunum,
_intrmap[i].pin,
......
/*
* GT641xx IRQ routines.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -652,6 +652,8 @@ einval: li v0, -ENOSYS
sys sys_inotify_init1 1
sys sys_preadv 6 /* 4330 */
sys sys_pwritev 6
sys sys_rt_tgsigqueueinfo 4
sys sys_perf_counter_open 5
.endm
/* We pre-compute the number of _instruction_ bytes needed to
......
......@@ -489,4 +489,6 @@ sys_call_table:
PTR sys_inotify_init1
PTR sys_preadv
PTR sys_pwritev /* 5390 */
PTR sys_rt_tgsigqueueinfo
PTR sys_perf_counter_open
.size sys_call_table,.-sys_call_table
......@@ -415,4 +415,6 @@ EXPORT(sysn32_call_table)
PTR sys_inotify_init1
PTR sys_preadv
PTR sys_pwritev
PTR compat_sys_rt_tgsigqueueinfo /* 5295 */
PTR sys_perf_counter_open
.size sysn32_call_table,.-sysn32_call_table
......@@ -535,4 +535,6 @@ sys_call_table:
PTR sys_inotify_init1
PTR compat_sys_preadv /* 4330 */
PTR compat_sys_pwritev
PTR compat_sys_rt_tgsigqueueinfo
PTR sys_perf_counter_open
.size sys_call_table,.-sys_call_table
......@@ -37,80 +37,24 @@
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
/*
* Crude manipulation of the CPU masks to control which
* which CPU's are brought online during initialisation
*
* Beware... this needs to be called after CPU discovery
* but before CPU bringup
*/
static int __init allowcpus(char *str)
{
cpumask_t cpu_allow_map;
char buf[256];
int len;
cpus_clear(cpu_allow_map);
if (cpulist_parse(str, &cpu_allow_map) == 0) {
cpu_set(0, cpu_allow_map);
cpus_and(cpu_possible_map, cpu_possible_map, cpu_allow_map);
len = cpulist_scnprintf(buf, sizeof(buf)-1, &cpu_possible_map);
buf[len] = '\0';
pr_debug("Allowable CPUs: %s\n", buf);
return 1;
} else
return 0;
}
__setup("allowcpus=", allowcpus);
#include <asm/amon.h>
#include <asm/gic.h>
static void ipi_call_function(unsigned int cpu)
{
unsigned int action = 0;
pr_debug("CPU%d: %s cpu %d status %08x\n",
smp_processor_id(), __func__, cpu, read_c0_status());
switch (cpu) {
case 0:
action = GIC_IPI_EXT_INTR_CALLFNC_VPE0;
break;
case 1:
action = GIC_IPI_EXT_INTR_CALLFNC_VPE1;
break;
case 2:
action = GIC_IPI_EXT_INTR_CALLFNC_VPE2;
break;
case 3:
action = GIC_IPI_EXT_INTR_CALLFNC_VPE3;
break;
}
gic_send_ipi(action);
gic_send_ipi(plat_ipi_call_int_xlate(cpu));
}
static void ipi_resched(unsigned int cpu)
{
unsigned int action = 0;
pr_debug("CPU%d: %s cpu %d status %08x\n",
smp_processor_id(), __func__, cpu, read_c0_status());
switch (cpu) {
case 0:
action = GIC_IPI_EXT_INTR_RESCHED_VPE0;
break;
case 1:
action = GIC_IPI_EXT_INTR_RESCHED_VPE1;
break;
case 2:
action = GIC_IPI_EXT_INTR_RESCHED_VPE2;
break;
case 3:
action = GIC_IPI_EXT_INTR_RESCHED_VPE3;
break;
}
gic_send_ipi(action);
gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
}
/*
......@@ -206,7 +150,7 @@ static void cmp_boot_secondary(int cpu, struct task_struct *idle)
(unsigned long)(gp + sizeof(struct thread_info)));
#endif
amon_cpu_start(cpu, pc, sp, gp, a0);
amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
}
/*
......
/*
* Count register synchronisation.
*
* All CPUs will have their count registers synchronised to the CPU0 expirelo
* All CPUs will have their count registers synchronised to the CPU0 next time
* value. This can cause a small timewarp for CPU0. All other CPU's should
* not have done anything significant (but they may have had interrupts
* enabled briefly - prom_smp_finish() should not be responsible for enabling
......@@ -13,21 +13,22 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irqflags.h>
#include <linux/r4k-timer.h>
#include <linux/cpumask.h>
#include <asm/r4k-timer.h>
#include <asm/atomic.h>
#include <asm/barrier.h>
#include <asm/cpumask.h>
#include <asm/mipsregs.h>
static atomic_t __initdata count_start_flag = ATOMIC_INIT(0);
static atomic_t __initdata count_count_start = ATOMIC_INIT(0);
static atomic_t __initdata count_count_stop = ATOMIC_INIT(0);
static atomic_t __cpuinitdata count_start_flag = ATOMIC_INIT(0);
static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0);
static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
#define COUNTON 100
#define NR_LOOPS 5
void __init synchronise_count_master(void)
void __cpuinit synchronise_count_master(void)
{
int i;
unsigned long flags;
......@@ -42,19 +43,20 @@ void __init synchronise_count_master(void)
return;
#endif
pr_info("Checking COUNT synchronization across %u CPUs: ",
num_online_cpus());
printk(KERN_INFO "Synchronize counters across %u CPUs: ",
num_online_cpus());
local_irq_save(flags);
/*
* Notify the slaves that it's time to start
*/
atomic_set(&count_reference, read_c0_count());
atomic_set(&count_start_flag, 1);
smp_wmb();
/* Count will be initialised to expirelo for all CPU's */
initcount = expirelo;
/* Count will be initialised to current timer for all CPU's */
initcount = read_c0_count();
/*
* We loop a few times to get a primed instruction cache,
......@@ -106,7 +108,7 @@ void __init synchronise_count_master(void)
printk("done.\n");
}
void __init synchronise_count_slave(void)
void __cpuinit synchronise_count_slave(void)
{
int i;
unsigned long flags;
......@@ -131,8 +133,8 @@ void __init synchronise_count_slave(void)
while (!atomic_read(&count_start_flag))
mb();
/* Count will be initialised to expirelo for all CPU's */
initcount = expirelo;
/* Count will be initialised to next expire for all CPU's */
initcount = atomic_read(&count_reference);
ncpus = num_online_cpus();
for (i = 0; i < NR_LOOPS; i++) {
......@@ -156,4 +158,3 @@ void __init synchronise_count_slave(void)
local_irq_restore(flags);
}
#undef NR_LOOPS
#endif
......@@ -1387,7 +1387,7 @@ static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr,
return len;
out_einval:
return -EINVAL;;
return -EINVAL;
}
static struct device_attribute vpe_class_attributes[] = {
......
......@@ -30,6 +30,7 @@
#include <asm/cacheflush.h>
#include <asm/traps.h>
#include <asm/gcmpregs.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/bonito64.h>
......@@ -192,6 +193,8 @@ extern struct plat_smp_ops msmtc_smp_ops;
void __init prom_init(void)
{
int result;
prom_argc = fw_arg0;
_prom_argv = (int *) fw_arg1;
_prom_envp = (int *) fw_arg2;
......@@ -358,12 +361,21 @@ void __init prom_init(void)
#ifdef CONFIG_SERIAL_8250_CONSOLE
console_config();
#endif
/* Early detection of CMP support */
result = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
#ifdef CONFIG_MIPS_CMP
register_smp_ops(&cmp_smp_ops);
if (result)
register_smp_ops(&cmp_smp_ops);
#endif
#ifdef CONFIG_MIPS_MT_SMP
#ifdef CONFIG_MIPS_CMP
if (!result)
register_smp_ops(&vsmp_smp_ops);
#else
register_smp_ops(&vsmp_smp_ops);
#endif
#endif
#ifdef CONFIG_MIPS_MT_SMTC
register_smp_ops(&msmtc_smp_ops);
#endif
......
......@@ -331,6 +331,21 @@ static struct irqaction irq_call = {
.flags = IRQF_DISABLED|IRQF_PERCPU,
.name = "IPI_call"
};
static int gic_resched_int_base;
static int gic_call_int_base;
#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
{
return GIC_CALL_INT(cpu);
}
unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
{
return GIC_RESCHED_INT(cpu);
}
#endif /* CONFIG_MIPS_MT_SMP */
static struct irqaction i8259irq = {
......@@ -370,7 +385,7 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
* Interrupts and CPUs/Core Interrupts. The nature of the External
* Interrupts is also defined here - polarity/trigger.
*/
static struct gic_intr_map gic_intr_map[] = {
static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
{ GIC_EXT_INTR(0), X, X, X, X, 0 },
{ GIC_EXT_INTR(1), X, X, X, X, 0 },
{ GIC_EXT_INTR(2), X, X, X, X, 0 },
......@@ -387,21 +402,14 @@ static struct gic_intr_map gic_intr_map[] = {
{ GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
{ GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
{ GIC_EXT_INTR(15), X, X, X, X, 0 },
{ GIC_EXT_INTR(16), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(17), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(18), 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(19), 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(20), 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(21), 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(22), 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
{ GIC_EXT_INTR(23), 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, 1 },
/* This is the end of the general interrupts now we do IPI ones */
};
#endif
/*
* GCMP needs to be detected before any SMP initialisation
*/
static int __init gcmp_probe(unsigned long addr, unsigned long size)
int __init gcmp_probe(unsigned long addr, unsigned long size)
{
if (gcmp_present >= 0)
return gcmp_present;
......@@ -416,28 +424,36 @@ static int __init gcmp_probe(unsigned long addr, unsigned long size)
}
#if defined(CONFIG_MIPS_MT_SMP)
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
{
int intr = baseintr + cpu;
gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
gic_intr_map[intr].cpunum = cpu;
gic_intr_map[intr].pin = cpupin;
gic_intr_map[intr].polarity = GIC_POL_POS;
gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
gic_intr_map[intr].ipiflag = 1;
ipi_map[cpu] |= (1 << (cpupin + 2));
}
static void __init fill_ipi_map(void)
{
int i;
int cpu;
for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X))
ipi_map[gic_intr_map[i].cpunum] |=
(1 << (gic_intr_map[i].pin + 2));
for (cpu = 0; cpu < NR_CPUS; cpu++) {
fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
}
}
#endif
void __init arch_init_irq(void)
{
int gic_present, gcmp_present;
init_i8259_irqs();
if (!cpu_has_veic)
mips_cpu_irq_init();
gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
if (gcmp_present) {
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
gic_present = 1;
......@@ -514,24 +530,10 @@ void __init arch_init_irq(void)
if (gic_present) {
/* FIXME */
int i;
struct {
unsigned int resched;
unsigned int call;
} ipiirq[] = {
{
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE0,
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE0},
{
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE1,
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE1
}, {
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE2,
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE2
}, {
.resched = GIC_IPI_EXT_INTR_RESCHED_VPE3,
.call = GIC_IPI_EXT_INTR_CALLFNC_VPE3
}
};
gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
gic_resched_int_base = gic_call_int_base - NR_CPUS;
fill_ipi_map();
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
if (!gcmp_present) {
......@@ -553,12 +555,15 @@ void __init arch_init_irq(void)
printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
write_c0_status(0x1100dc00);
printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
for (i = 0; i < ARRAY_SIZE(ipiirq); i++) {
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq);
set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq);
for (i = 0; i < NR_CPUS; i++) {
setup_irq(MIPS_GIC_IRQ_BASE +
GIC_RESCHED_INT(i), &irq_resched);
setup_irq(MIPS_GIC_IRQ_BASE +
GIC_CALL_INT(i), &irq_call);
set_irq_handler(MIPS_GIC_IRQ_BASE +
GIC_RESCHED_INT(i), handle_percpu_irq);
set_irq_handler(MIPS_GIC_IRQ_BASE +
GIC_CALL_INT(i), handle_percpu_irq);
}
} else {
/* set up ipi interrupts */
......
......@@ -28,9 +28,6 @@
#include <asm/reboot.h>
#include <asm/mips-boards/generic.h>
static void mips_machine_restart(char *command);
static void mips_machine_halt(void);
static void mips_machine_restart(char *command)
{
unsigned int __iomem *softres_reg =
......
......@@ -52,3 +52,8 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
ifdef CONFIG_PCI_MSI
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
endif
/*
* fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups.
*
* Copyright (C) 2002,2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* fixup-mpc30x.c, The Victor MP-C303/304 specific PCI fixups.
*
* Copyright (C) 2002,2004 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -2,7 +2,7 @@
* fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
*
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
*
* Copyright (C) 2002-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
*
* Copyright (C) 2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
* Copyright (C) 2005-2009 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
......@@ -16,8 +16,7 @@
#include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include "pci-common.h"
#include <asm/octeon/pci-octeon.h>
/*
* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
......@@ -47,8 +46,8 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
* programming the MSI control bits [6:4] before calling
* pci_enable_msi().
*
* @param dev Device requesting MSI interrupts
* @param desc MSI descriptor
* @dev: Device requesting MSI interrupts
* @desc: MSI descriptor
*
* Returns 0 on success.
*/
......@@ -213,14 +212,9 @@ void arch_teardown_msi_irq(unsigned int irq)
}
/**
/*
* Called by the interrupt handling code when an MSI interrupt
* occurs.
*
* @param cpl
* @param dev_id
*
* @return
*/
static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
{
......@@ -256,31 +250,37 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
}
/**
/*
* Initializes the MSI interrupt handling code
*
* @return
*/
int octeon_msi_initialize(void)
{
int r;
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[0:63]", octeon_msi_interrupt);
"MSI[0:63]", octeon_msi_interrupt))
panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
} else if (octeon_is_pci_host()) {
r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[0:15]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[16:31]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[32:47]", octeon_msi_interrupt);
r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[48:63]", octeon_msi_interrupt);
"MSI[0:15]", octeon_msi_interrupt))
panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[16:31]", octeon_msi_interrupt))
panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[32:47]", octeon_msi_interrupt))
panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
IRQF_SHARED,
"MSI[48:63]", octeon_msi_interrupt))
panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
}
return 0;
}
......
......@@ -2,8 +2,8 @@
* ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
*
* Copyright (C) 2001-2003 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -21,7 +21,7 @@
*/
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
* MontaVista Software Inc. <source@mvista.com>
* - New creation, NEC VR4122 and VR4131 are supported.
*/
#include <linux/pci.h>
......
......@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005-2007 Cavium Networks
* Copyright (C) 2005-2009 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
......@@ -17,8 +17,7 @@
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>
#include "pci-common.h"
#include <asm/octeon/pci-octeon.h>
#define USE_OCTEON_INTERNAL_ARBITER
......@@ -54,6 +53,126 @@ union octeon_pci_address {
} s;
};
int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
u8 slot, u8 pin);
enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
/**
* Map a PCI device to the appropriate interrupt line
*
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @pin: The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* Returns Interrupt number for the device
*/
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (octeon_pcibios_map_irq)
return octeon_pcibios_map_irq(dev, slot, pin);
else
panic("octeon_pcibios_map_irq not set.");
}
/*
* Called to perform platform specific PCI setup
*/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
uint16_t config;
uint32_t dconfig;
int pos;
/*
* Force the Cache line setting to 64 bytes. The standard
* Linux bus scan doesn't seem to set it. Octeon really has
* 128 byte lines, but Intel bridges get really upset if you
* try and set values above 64 bytes. Value is specified in
* 32bit words.
*/
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
/* Set latency timers for all devices */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
/* Enable reporting System errors and parity errors on all devices */
/* Enable parity checking and error reporting */
pci_read_config_word(dev, PCI_COMMAND, &config);
config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
pci_write_config_word(dev, PCI_COMMAND, config);
if (dev->subordinate) {
/* Set latency timers on sub bridges */
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
/* More bridge error detection */
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
}
/* Enable the PCIe normal error reporting */
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pos) {
/* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
/* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_CERE;
/* Non-Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE;
/* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE;
/* Unsupported Request */
config |= PCI_EXP_DEVCTL_URRE;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
}
/* Find the Advanced Error Reporting capability */
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
if (pos) {
/* Clear Uncorrectable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
&dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
dconfig);
/* Enable reporting of all uncorrectable errors */
/* Uncorrectable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
/*
* Leave severity at HW default. This only controls if
* errors are reported as uncorrectable or
* correctable, not if the error is reported.
*/
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
/* Clear Correctable Error Status */
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
/* Enable reporting of all correctable errors */
/* Correctable Error Mask - turned on bits disable errors */
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
/* Advanced Error Capabilities */
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
/* ECRC Generation Enable */
if (config & PCI_ERR_CAP_ECRC_GENC)
config |= PCI_ERR_CAP_ECRC_GENE;
/* ECRC Check Enable */
if (config & PCI_ERR_CAP_ECRC_CHKC)
config |= PCI_ERR_CAP_ECRC_CHKE;
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
/* Report all errors to the root complex */
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
PCI_ERR_ROOT_CMD_COR_EN |
PCI_ERR_ROOT_CMD_NONFATAL_EN |
PCI_ERR_ROOT_CMD_FATAL_EN);
/* Clear the Root status register */
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
}
return 0;
}
/**
* Return the mapping of PCI device number to IRQ line. Each
* character in the return string represents the interrupt
......@@ -136,9 +255,8 @@ int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
}
/**
/*
* Read a value from configuration space
*
*/
static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 *val)
......@@ -174,15 +292,8 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
}
/**
/*
* Write a value to PCI configuration space
*
* @bus:
* @devfn:
* @reg:
* @size:
* @val:
* Returns
*/
static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
int reg, int size, u32 val)
......@@ -251,10 +362,8 @@ static struct pci_controller octeon_pci_controller = {
};
/**
/*
* Low level initialize the Octeon PCI controller
*
* Returns
*/
static void octeon_pci_initialize(void)
{
......@@ -398,7 +507,7 @@ static void octeon_pci_initialize(void)
pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
}
#endif /* USE_OCTEON_INTERNAL_ARBITER */
#endif /* USE_OCTEON_INTERNAL_ARBITER */
/*
* Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
......@@ -457,10 +566,8 @@ static void octeon_pci_initialize(void)
}
/**
/*
* Initialize the Octeon PCI controller
*
* Returns
*/
static int __init octeon_pci_setup(void)
{
......
......@@ -2,8 +2,8 @@
* pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series.
*
* Copyright (C) 2001-2003 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copyright (C) 2004-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify
......@@ -22,7 +22,7 @@
*/
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
* MontaVista Software Inc. <source@mvista.com>
* - New creation, NEC VR4122 and VR4131 are supported.
*/
#include <linux/init.h>
......
......@@ -2,8 +2,8 @@
* pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
*
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copyright (C) 2004-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -18,8 +18,7 @@
#include <asm/octeon/cvmx-pescx-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
#include <asm/octeon/cvmx-helper-errata.h>
#include "pci-common.h"
#include <asm/octeon/pci-octeon.h>
union cvmx_pcie_address {
uint64_t u64;
......@@ -976,13 +975,13 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
/**
* Map a PCI device to the appropriate interrupt line
*
* @param dev The Linux PCI device structure for the device to map
* @param slot The slot number for this device on __BUS 0__. Linux
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @param pin The PCI interrupt pin read from the device, then swizzled
* @pin: The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* @return Interrupt number for the device
* Returns Interrupt number for the device
*/
int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
u8 slot, u8 pin)
......@@ -1025,12 +1024,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
/**
* Read a value from configuration space
*
* @param bus
* @param devfn
* @param reg
* @param size
* @param val
* @return
* @bus:
* @devfn:
* @reg:
* @size:
* @val:
* Returns
*/
static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
unsigned int devfn, int reg, int size,
......@@ -1156,12 +1155,12 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
/**
* Write a value to PCI configuration space
*
* @param bus
* @param devfn
* @param reg
* @param size
* @param val
* @return
* @bus:
* @devfn:
* @reg:
* @size:
* @val:
* Returns
*/
static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
unsigned int devfn, int reg,
......@@ -1254,7 +1253,7 @@ static struct pci_controller octeon_pcie1_controller = {
/**
* Initialize the Octeon PCIe controllers
*
* @return
* Returns
*/
static int __init octeon_pcie_setup(void)
{
......
/*
* setup.c, Setup for the CASIO CASSIOPEIA E-11/15/55/65.
*
* Copyright (C) 2002-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2002-2006 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -2,8 +2,8 @@
* bcu.c, Bus Control Unit routines for the NEC VR4100 series.
*
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com>
* Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -21,11 +21,11 @@
*/
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
* MontaVista Software Inc. <source@mvista.com>
* - New creation, NEC VR4122 and VR4131 are supported.
* - Added support for NEC VR4111 and VR4121.
*
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Yoichi Yuasa <yuasa@linux-mips.org>
* - Added support for NEC VR4133.
*/
#include <linux/kernel.h>
......
......@@ -2,8 +2,8 @@
* cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
*
* Copyright (C) 2001-2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copuright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copuright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -21,11 +21,11 @@
*/
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
* MontaVista Software Inc. <source@mvista.com>
* - New creation, NEC VR4122 and VR4131 are supported.
* - Added support for NEC VR4111 and VR4121.
*
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Yoichi Yuasa <yuasa@linux-mips.org>
* - Added support for NEC VR4133.
*/
#include <linux/init.h>
......
/*
* NEC VR4100 series GIU platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
......@@ -2,8 +2,8 @@
* icu.c, Interrupt Control Unit routines for the NEC VR4100 series.
*
* Copyright (C) 2001-2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -21,11 +21,11 @@
*/
/*
* Changes:
* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
* MontaVista Software Inc. <source@mvista.com>
* - New creation, NEC VR4122 and VR4131 are supported.
* - Added support for NEC VR4111 and VR4121.
*
* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Yoichi Yuasa <yuasa@linux-mips.org>
* - Coped with INTASSIGN of NEC VR4133.
*/
#include <linux/errno.h>
......
/*
* init.c, Common initialization routines for NEC VR4100 series.
*
* Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* Interrupt handing routines for NEC VR4100 series.
*
* Copyright (C) 2005-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* pmu.c, Power Management Unit routines for NEC VR4100 series.
*
* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2003-2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* NEC VR4100 series RTC platform device.
*
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
/*
* NEC VR4100 series SIU platform device.
*
* Copyright (C) 2007-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
* Copyright (C) 2007-2008 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......
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