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Commit 493d5f6d authored by David S. Miller's avatar David S. Miller
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Merge branch 'r8152-phy-fixes' 

Hayes Wang says:

====================
r8152: correct the flow of PHY

First, to enable the PHY as early as possible. Some settings may fail if the
PHY is power down.

Move the other PHY settings to hw_phy_cfg() to make sure the order is correct.

Finally, disable ALDPS and EEE before updating the PHY for RTL8153.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 9b86a8d1 d768c61b
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Showing with 146 additions and 135 deletions
drivers/net/usb/r8152.c
View file @ 493d5f6d
......@@ -32,7 +32,7 @@
#define NETNEXT_VERSION "08"
/* Information for net */
#define NET_VERSION "5"
#define NET_VERSION "6"
#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
......@@ -2552,6 +2552,77 @@ static void r8152_aldps_en(struct r8152 *tp, bool enable)
}
}
static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
{
ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
ocp_reg_write(tp, OCP_EEE_DATA, reg);
ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
}
static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
{
u16 data;
r8152_mmd_indirect(tp, dev, reg);
data = ocp_reg_read(tp, OCP_EEE_DATA);
ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
return data;
}
static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
{
r8152_mmd_indirect(tp, dev, reg);
ocp_reg_write(tp, OCP_EEE_DATA, data);
ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
}
static void r8152_eee_en(struct r8152 *tp, bool enable)
{
u16 config1, config2, config3;
u32 ocp_data;
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
if (enable) {
ocp_data |= EEE_RX_EN | EEE_TX_EN;
config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
config1 |= sd_rise_time(1);
config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
config3 |= fast_snr(42);
} else {
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
RX_QUIET_EN);
config1 |= sd_rise_time(7);
config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
config3 |= fast_snr(511);
}
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
}
static void r8152b_enable_eee(struct r8152 *tp)
{
r8152_eee_en(tp, true);
r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
}
static void r8152b_enable_fc(struct r8152 *tp)
{
u16 anar;
anar = r8152_mdio_read(tp, MII_ADVERTISE);
anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
r8152_mdio_write(tp, MII_ADVERTISE, anar);
}
static void rtl8152_disable(struct r8152 *tp)
{
r8152_aldps_en(tp, false);
......@@ -2561,13 +2632,9 @@ static void rtl8152_disable(struct r8152 *tp)
static void r8152b_hw_phy_cfg(struct r8152 *tp)
{
u16 data;
data = r8152_mdio_read(tp, MII_BMCR);
if (data & BMCR_PDOWN) {
data &= ~BMCR_PDOWN;
r8152_mdio_write(tp, MII_BMCR, data);
}
r8152b_enable_eee(tp);
r8152_aldps_en(tp, true);
r8152b_enable_fc(tp);
set_bit(PHY_RESET, &tp->flags);
}
......@@ -2701,20 +2768,52 @@ static void r8152b_enter_oob(struct r8152 *tp)
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
}
static void r8153_aldps_en(struct r8152 *tp, bool enable)
{
u16 data;
data = ocp_reg_read(tp, OCP_POWER_CFG);
if (enable) {
data |= EN_ALDPS;
ocp_reg_write(tp, OCP_POWER_CFG, data);
} else {
data &= ~EN_ALDPS;
ocp_reg_write(tp, OCP_POWER_CFG, data);
msleep(20);
}
}
static void r8153_eee_en(struct r8152 *tp, bool enable)
{
u32 ocp_data;
u16 config;
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
config = ocp_reg_read(tp, OCP_EEE_CFG);
if (enable) {
ocp_data |= EEE_RX_EN | EEE_TX_EN;
config |= EEE10_EN;
} else {
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
config &= ~EEE10_EN;
}
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
ocp_reg_write(tp, OCP_EEE_CFG, config);
}
static void r8153_hw_phy_cfg(struct r8152 *tp)
{
u32 ocp_data;
u16 data;
if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
tp->version == RTL_VER_05)
ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
/* disable ALDPS before updating the PHY parameters */
r8153_aldps_en(tp, false);
data = r8152_mdio_read(tp, MII_BMCR);
if (data & BMCR_PDOWN) {
data &= ~BMCR_PDOWN;
r8152_mdio_write(tp, MII_BMCR, data);
}
/* disable EEE before updating the PHY parameters */
r8153_eee_en(tp, false);
ocp_reg_write(tp, OCP_EEE_ADV, 0);
if (tp->version == RTL_VER_03) {
data = ocp_reg_read(tp, OCP_EEE_CFG);
......@@ -2745,6 +2844,12 @@ static void r8153_hw_phy_cfg(struct r8152 *tp)
sram_write(tp, SRAM_10M_AMP1, 0x00af);
sram_write(tp, SRAM_10M_AMP2, 0x0208);
r8153_eee_en(tp, true);
ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
r8153_aldps_en(tp, true);
r8152b_enable_fc(tp);
set_bit(PHY_RESET, &tp->flags);
}
......@@ -2866,21 +2971,6 @@ static void r8153_enter_oob(struct r8152 *tp)
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
}
static void r8153_aldps_en(struct r8152 *tp, bool enable)
{
u16 data;
data = ocp_reg_read(tp, OCP_POWER_CFG);
if (enable) {
data |= EN_ALDPS;
ocp_reg_write(tp, OCP_POWER_CFG, data);
} else {
data &= ~EN_ALDPS;
ocp_reg_write(tp, OCP_POWER_CFG, data);
msleep(20);
}
}
static void rtl8153_disable(struct r8152 *tp)
{
r8153_aldps_en(tp, false);
......@@ -3246,103 +3336,6 @@ static int rtl8152_close(struct net_device *netdev)
return res;
}
static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
{
ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
ocp_reg_write(tp, OCP_EEE_DATA, reg);
ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
}
static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
{
u16 data;
r8152_mmd_indirect(tp, dev, reg);
data = ocp_reg_read(tp, OCP_EEE_DATA);
ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
return data;
}
static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
{
r8152_mmd_indirect(tp, dev, reg);
ocp_reg_write(tp, OCP_EEE_DATA, data);
ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
}
static void r8152_eee_en(struct r8152 *tp, bool enable)
{
u16 config1, config2, config3;
u32 ocp_data;
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
if (enable) {
ocp_data |= EEE_RX_EN | EEE_TX_EN;
config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
config1 |= sd_rise_time(1);
config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
config3 |= fast_snr(42);
} else {
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
RX_QUIET_EN);
config1 |= sd_rise_time(7);
config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
config3 |= fast_snr(511);
}
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
}
static void r8152b_enable_eee(struct r8152 *tp)
{
r8152_eee_en(tp, true);
r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
}
static void r8153_eee_en(struct r8152 *tp, bool enable)
{
u32 ocp_data;
u16 config;
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
config = ocp_reg_read(tp, OCP_EEE_CFG);
if (enable) {
ocp_data |= EEE_RX_EN | EEE_TX_EN;
config |= EEE10_EN;
} else {
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
config &= ~EEE10_EN;
}
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
ocp_reg_write(tp, OCP_EEE_CFG, config);
}
static void r8153_enable_eee(struct r8152 *tp)
{
r8153_eee_en(tp, true);
ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
}
static void r8152b_enable_fc(struct r8152 *tp)
{
u16 anar;
anar = r8152_mdio_read(tp, MII_ADVERTISE);
anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
r8152_mdio_write(tp, MII_ADVERTISE, anar);
}
static void rtl_tally_reset(struct r8152 *tp)
{
u32 ocp_data;
......@@ -3355,10 +3348,17 @@ static void rtl_tally_reset(struct r8152 *tp)
static void r8152b_init(struct r8152 *tp)
{
u32 ocp_data;
u16 data;
if (test_bit(RTL8152_UNPLUG, &tp->flags))
return;
data = r8152_mdio_read(tp, MII_BMCR);
if (data & BMCR_PDOWN) {
data &= ~BMCR_PDOWN;
r8152_mdio_write(tp, MII_BMCR, data);
}
r8152_aldps_en(tp, false);
if (tp->version == RTL_VER_01) {
......@@ -3380,9 +3380,6 @@ static void r8152b_init(struct r8152 *tp)
SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
r8152b_enable_eee(tp);
r8152_aldps_en(tp, true);
r8152b_enable_fc(tp);
rtl_tally_reset(tp);
/* enable rx aggregation */
......@@ -3394,12 +3391,12 @@ static void r8152b_init(struct r8152 *tp)
static void r8153_init(struct r8152 *tp)
{
u32 ocp_data;
u16 data;
int i;
if (test_bit(RTL8152_UNPLUG, &tp->flags))
return;
r8153_aldps_en(tp, false);
r8153_u1u2en(tp, false);
for (i = 0; i < 500; i++) {
......@@ -3416,6 +3413,23 @@ static void r8153_init(struct r8152 *tp)
msleep(20);
}
if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
tp->version == RTL_VER_05)
ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
data = r8152_mdio_read(tp, MII_BMCR);
if (data & BMCR_PDOWN) {
data &= ~BMCR_PDOWN;
r8152_mdio_write(tp, MII_BMCR, data);
}
for (i = 0; i < 500; i++) {
ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
if (ocp_data == PHY_STAT_LAN_ON)
break;
msleep(20);
}
usb_disable_lpm(tp->udev);
r8153_u2p3en(tp, false);
......@@ -3483,9 +3497,6 @@ static void r8153_init(struct r8152 *tp)
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
r8153_enable_eee(tp);
r8153_aldps_en(tp, true);
r8152b_enable_fc(tp);
rtl_tally_reset(tp);
r8153_u2p3en(tp, true);
}
......
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