Commit 49f2a554 authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman

staging: r8188eu: Remove wrapper rtw_udelay_os()

This wrapper is a simple call to udelay(). Remove it.
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Link: https://lore.kernel.org/r/20210805192644.15978-4-Larry.Finger@lwfinger.netSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e72e1495
...@@ -186,7 +186,7 @@ ReadEFuseByte( ...@@ -186,7 +186,7 @@ ReadEFuseByte(
/* This fix the problem that Efuse read error in high temperature condition. */ /* This fix the problem that Efuse read error in high temperature condition. */
/* Designer says that there shall be some delay after ready bit is set, or the */ /* Designer says that there shall be some delay after ready bit is set, or the */
/* result will always stay on last data we read. */ /* result will always stay on last data we read. */
rtw_udelay_os(50); udelay(50);
value32 = rtw_read32(Adapter, EFUSE_CTRL); value32 = rtw_read32(Adapter, EFUSE_CTRL);
*pbuf = (u8)(value32 & 0xff); *pbuf = (u8)(value32 & 0xff);
......
...@@ -66,7 +66,7 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, ...@@ -66,7 +66,7 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd))) if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
poll_bit = true; poll_bit = true;
else else
rtw_udelay_os(10); udelay(10);
if (poll_count++ > max_poll_count) { if (poll_count++ > max_poll_count) {
DBG_88E("Fail to polling Offset[%#x]\n", offset); DBG_88E("Fail to polling Offset[%#x]\n", offset);
...@@ -76,9 +76,9 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers, ...@@ -76,9 +76,9 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
break; break;
case PWR_CMD_DELAY: case PWR_CMD_DELAY:
if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US) if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)); udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
else else
rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000); udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
break; break;
case PWR_CMD_END: case PWR_CMD_END:
/* When this command is parsed, end the process */ /* When this command is parsed, end the process */
......
...@@ -132,7 +132,7 @@ void ODM_IsWorkItemScheduled(void *pRtWorkItem) ...@@ -132,7 +132,7 @@ void ODM_IsWorkItemScheduled(void *pRtWorkItem)
/* ODM Timer relative API. */ /* ODM Timer relative API. */
void ODM_StallExecution(u32 usDelay) void ODM_StallExecution(u32 usDelay)
{ {
rtw_udelay_os(usDelay); udelay(usDelay);
} }
void ODM_delay_ms(u32 ms) void ODM_delay_ms(u32 ms)
...@@ -142,7 +142,7 @@ void ODM_delay_ms(u32 ms) ...@@ -142,7 +142,7 @@ void ODM_delay_ms(u32 ms)
void ODM_delay_us(u32 us) void ODM_delay_us(u32 us)
{ {
rtw_udelay_os(us); udelay(us);
} }
void ODM_sleep_ms(u32 ms) void ODM_sleep_ms(u32 ms)
......
...@@ -533,7 +533,7 @@ static s32 _FWFreeToGo(struct adapter *padapter) ...@@ -533,7 +533,7 @@ static s32 _FWFreeToGo(struct adapter *padapter)
DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32); DBG_88E("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __func__, value32);
return _SUCCESS; return _SUCCESS;
} }
rtw_udelay_os(5); udelay(5);
} while (counter++ < POLLING_READY_TIMEOUT_COUNT); } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32); DBG_88E("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __func__, value32);
......
...@@ -170,12 +170,12 @@ phy_RFSerialRead( ...@@ -170,12 +170,12 @@ phy_RFSerialRead(
tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
rtw_udelay_os(10);/* PlatformStallExecution(10); */ udelay(10);/* PlatformStallExecution(10); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
rtw_udelay_os(100);/* PlatformStallExecution(100); */ udelay(100);/* PlatformStallExecution(100); */
rtw_udelay_os(10);/* PlatformStallExecution(10); */ udelay(10);/* PlatformStallExecution(10); */
if (eRFPath == RF_PATH_A) if (eRFPath == RF_PATH_A)
RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
......
...@@ -480,18 +480,18 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) ...@@ -480,18 +480,18 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
} }
/*----Set RF_ENV enable----*/ /*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/ /*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */ /* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */ udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/ /*----Initialize RF fom connfiguration file----*/
switch (eRFPath) { switch (eRFPath) {
......
...@@ -236,8 +236,6 @@ void rtw_usleep_os(int us); ...@@ -236,8 +236,6 @@ void rtw_usleep_os(int us);
u32 rtw_atoi(u8 *s); u32 rtw_atoi(u8 *s);
void rtw_udelay_os(int us);
static inline unsigned char _cancel_timer_ex(struct timer_list *ptimer) static inline unsigned char _cancel_timer_ex(struct timer_list *ptimer)
{ {
return del_timer_sync(ptimer); return del_timer_sync(ptimer);
......
...@@ -141,11 +141,6 @@ void rtw_usleep_os(int us) ...@@ -141,11 +141,6 @@ void rtw_usleep_os(int us)
msleep((us/1000) + 1); msleep((us/1000) + 1);
} }
void rtw_udelay_os(int us)
{
udelay((unsigned long)us);
}
#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" #define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
static const struct device_type wlan_type = { static const struct device_type wlan_type = {
......
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