Commit 4af184ee authored by Len Brown's avatar Len Brown

tools/power turbostat: dump secondary Turbo-Ratio-Limit

Intel Performance Hybrid processors have a 2nd MSR
describing the turbo limits enforced on the Ecores.

Note, TRL and Secondary-TRL are usually R/O information,
but on overclock-capable parts, they can be written.
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 5d622845
......@@ -388,6 +388,7 @@
#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
......
......@@ -2529,13 +2529,14 @@ int has_turbo_ratio_group_limits(int family, int model)
}
}
static void dump_turbo_ratio_limits(int family, int model)
static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model)
{
unsigned long long msr, core_counts;
int shift;
get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
get_msr(base_cpu, trl_msr_offset, &msr);
fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY" : "", msr);
if (has_turbo_ratio_group_limits(family, model)) {
get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
......@@ -4073,8 +4074,12 @@ static void dump_cstate_pstate_config_info(unsigned int family, unsigned int mod
if (has_ivt_turbo_ratio_limit(family, model))
dump_ivt_turbo_ratio_limits();
if (has_turbo_ratio_limit(family, model))
dump_turbo_ratio_limits(family, model);
if (has_turbo_ratio_limit(family, model)) {
dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model);
if (is_hybrid)
dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model);
}
if (has_atom_turbo_ratio_limit(family, model))
dump_atom_turbo_ratio_limits();
......
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