Commit 4c385b25 authored by Archit Taneja's avatar Archit Taneja Committed by Stephen Boyd

clk: qcom: Add EBI2 clocks for IPQ806x

The NAND controller within EBI2 requires EBI2_CLK and
EBI2_ALWAYS_ON_CLK clocks.  Create structs for these clocks so
that they can be used by the NAND controller driver. Add an entry
for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent f375573c
...@@ -2172,6 +2172,36 @@ static struct clk_branch usb_fs1_h_clk = { ...@@ -2172,6 +2172,36 @@ static struct clk_branch usb_fs1_h_clk = {
}, },
}; };
static struct clk_branch ebi2_clk = {
.hwcg_reg = 0x3b00,
.hwcg_bit = 6,
.halt_reg = 0x2fcc,
.halt_bit = 1,
.clkr = {
.enable_reg = 0x3b00,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ebi2_clk",
.ops = &clk_branch_ops,
.flags = CLK_IS_ROOT,
},
},
};
static struct clk_branch ebi2_aon_clk = {
.halt_reg = 0x2fcc,
.halt_bit = 0,
.clkr = {
.enable_reg = 0x3b00,
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "ebi2_always_on_clk",
.ops = &clk_branch_ops,
.flags = CLK_IS_ROOT,
},
},
};
static struct clk_regmap *gcc_ipq806x_clks[] = { static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr, [PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote, [PLL0_VOTE] = &pll0_vote,
...@@ -2275,6 +2305,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { ...@@ -2275,6 +2305,8 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
[EBI2_CLK] = &ebi2_clk.clkr,
[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
}; };
static const struct qcom_reset_map gcc_ipq806x_resets[] = { static const struct qcom_reset_map gcc_ipq806x_resets[] = {
......
...@@ -288,5 +288,6 @@ ...@@ -288,5 +288,6 @@
#define UBI32_CORE2_CLK_SRC 278 #define UBI32_CORE2_CLK_SRC 278
#define UBI32_CORE1_CLK 279 #define UBI32_CORE1_CLK 279
#define UBI32_CORE2_CLK 280 #define UBI32_CORE2_CLK 280
#define EBI2_AON_CLK 281
#endif #endif
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