Commit 50a5503a authored by Ben Dooks's avatar Ben Dooks Committed by Linus Torvalds

s3c-fb: initial move to unifying the header files

Remove the various header files that configure this driver and use the
platform device name to select the correct configuration at probe time.

Currently this does not remove the header files, only updates the driver
and the relevant platform files.
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarPawel Osciak <p.osciak@samsung.com>
Cc: InKi Dae <inki.dae@samsung.com>
Cc: KyungMin Park <kyungmin.park.samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 94947037
......@@ -18,24 +18,4 @@
#include <plat/regs-fb-v4.h>
/* Palette registers */
#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
#endif /* __ASM_ARCH_MACH_REGS_FB_H */
......@@ -100,40 +100,6 @@
#define BLENDCON (0x260)
#define BLENDCON_8BIT_ALPHA (1 << 0)
/* Per-window palette base addresses (start of palette memory).
* Each window palette area consists of 256 32-bit entries.
* START is the first address (entry 0th), END is the address of 255th entry.
*/
#define WIN0_PAL_BASE (0x2400)
#define WIN0_PAL_END (0x27fc)
#define WIN1_PAL_BASE (0x2800)
#define WIN1_PAL_END (0x2bfc)
#define WIN2_PAL_BASE (0x2c00)
#define WIN2_PAL_END (0x2ffc)
#define WIN3_PAL_BASE (0x3000)
#define WIN3_PAL_END (0x33fc)
#define WIN4_PAL_BASE (0x3400)
#define WIN4_PAL_END (0x37fc)
#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4))
#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4))
#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4))
#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4))
#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4))
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
#endif /* __ASM_ARCH_REGS_FB_H */
......@@ -148,42 +148,6 @@
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
......
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