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Commit 5375871d authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc merge from Benjamin Herrenschmidt:
 "Here's the powerpc batch for this merge window.  It is going to be a
  bit more nasty than usual as in touching things outside of
  arch/powerpc mostly due to the big iSeriesectomy :-) We finally got
  rid of the bugger (legacy iSeries support) which was a PITA to
  maintain and that nobody really used anymore.

  Here are some of the highlights:

   - Legacy iSeries is gone.  Thanks Stephen ! There's still some bits
     and pieces remaining if you do a grep -ir series arch/powerpc but
     they are harmless and will be removed in the next few weeks
     hopefully.

   - The 'fadump' functionality (Firmware Assisted Dump) replaces the
     previous (equivalent) "pHyp assisted dump"...  it's a rewrite of a
     mechanism to get the hypervisor to do crash dumps on pSeries, the
     new implementation hopefully being much more reliable.  Thanks
     Mahesh Salgaonkar.

   - The "EEH" code (pSeries PCI error handling & recovery) got a big
     spring cleaning, motivated by the need to be able to implement a
     new backend for it on top of some new different type of firwmare.

     The work isn't complete yet, but a good chunk of the cleanups is
     there.  Note that this adds a field to struct device_node which is
     not very nice and which Grant objects to.  I will have a patch soon
     that moves that to a powerpc private data structure (hopefully
     before rc1) and we'll improve things further later on (hopefully
     getting rid of the need for that pointer completely).  Thanks Gavin
     Shan.

   - I dug into our exception & interrupt handling code to improve the
     way we do lazy interrupt handling (and make it work properly with
     "edge" triggered interrupt sources), and while at it found & fixed
     a wagon of issues in those areas, including adding support for page
     fault retry & fatal signals on page faults.

   - Your usual random batch of small fixes & updates, including a bunch
     of new embedded boards, both Freescale and APM based ones, etc..."

I fixed up some conflicts with the generalized irq-domain changes from
Grant Likely, hopefully correctly.

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (141 commits)
  powerpc/ps3: Do not adjust the wrapper load address
  powerpc: Remove the rest of the legacy iSeries include files
  powerpc: Remove the remaining CONFIG_PPC_ISERIES pieces
  init: Remove CONFIG_PPC_ISERIES
  powerpc: Remove FW_FEATURE ISERIES from arch code
  tty/hvc_vio: FW_FEATURE_ISERIES is no longer selectable
  powerpc/spufs: Fix double unlocks
  powerpc/5200: convert mpc5200 to use of_platform_populate()
  powerpc/mpc5200: add options to mpc5200_defconfig
  powerpc/mpc52xx: add a4m072 board support
  powerpc/mpc5200: update mpc5200_defconfig to fit for charon board
  Documentation/powerpc/mpc52xx.txt: Checkpatch cleanup
  powerpc/44x: Add additional device support for APM821xx SoC and Bluestone board
  powerpc/44x: Add support PCI-E for APM821xx SoC and Bluestone board
  MAINTAINERS: Update PowerPC 4xx tree
  powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone board
  powerpc: document the FSL MPIC message register binding
  powerpc: add support for MPIC message register API
  powerpc/fsl: Added aliased MSIIR register address to MSI node in dts
  powerpc/85xx: mpc8548cds - add 36-bit dts
  ...
parents b57cb723 dfbc2d75
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Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt 0 → 100644
View file @ 5375871d
* FSL MPIC Message Registers
This binding specifies what properties must be available in the device tree
representation of the message register blocks found in some FSL MPIC
implementations.
Required properties:
- compatible: Specifies the compatibility list for the message register
block. The type shall be <string-list> and the value shall be of the form
"fsl,mpic-v<version>-msgr", where <version> is the version number of
the MPIC containing the message registers.
- reg: Specifies the base physical address(s) and size(s) of the
message register block's addressable register space. The type shall be
<prop-encoded-array>.
- interrupts: Specifies a list of interrupt-specifiers which are available
for receiving interrupts. Interrupt-specifier consists of two cells: first
cell is interrupt-number and second cell is level-sense. The type shall be
<prop-encoded-array>.
Optional properties:
- mpic-msgr-receive-mask: Specifies what registers in the containing block
are allowed to receive interrupts. The value is a bit mask where a set
bit at bit 'n' indicates that message register 'n' can receive interrupts.
Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
be <u32>. If not present, then all of the message registers in the block
are available.
Aliases:
An alias should be created for every message register block. They are not
required, though. However, a particular implementation of this binding
may require aliases to be present. Aliases are of the form
'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
Numbers shall start at 0.
Example:
aliases {
mpic-msgr-block0 = &mpic_msgr_block0;
mpic-msgr-block1 = &mpic_msgr_block1;
};
mpic_msgr_block0: mpic-msgr-block@41400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x41400 0x200>;
// Message registers 0 and 2 in this block can receive interrupts on
// sources 0xb0 and 0xb2, respectively.
interrupts = <0xb0 2 0xb2 2>;
mpic-msgr-receive-mask = <0x5>;
};
mpic_msgr_block1: mpic-msgr-block@42400 {
compatible = "fsl,mpic-v3.1-msgr";
reg = <0x42400 0x200>;
// Message registers 0 and 2 in this block can receive interrupts on
// sources 0xb4 and 0xb6, respectively.
interrupts = <0xb4 2 0xb6 2>;
mpic-msgr-receive-mask = <0x5>;
};
Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
View file @ 5375871d
......@@ -56,7 +56,27 @@ PROPERTIES
to the client. The presence of this property also mandates
that any initialization related to interrupt sources shall
be limited to sources explicitly referenced in the device tree.
- big-endian
Usage: optional
Value type: <empty>
If present the MPIC will be assumed to be big-endian. Some
device-trees omit this property on MPIC nodes even when the MPIC is
in fact big-endian, so certain boards override this property.
- single-cpu-affinity
Usage: optional
Value type: <empty>
If present the MPIC will be assumed to only be able to route
non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
- last-interrupt-source
Usage: optional
Value type: <u32>
Some MPICs do not correctly report the number of hardware sources
in the global feature registers. If specified, this field will
override the value read from MPIC_GREG_FEATURE_LAST_SRC.
INTERRUPT SPECIFIER DEFINITION
Interrupt specifiers consists of 4 cells encoded as
......
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
View file @ 5375871d
......@@ -6,8 +6,10 @@ Required properties:
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
the parent type.
- reg : should contain the address and the length of the shared message
interrupt register set.
- reg : It may contain one or two regions. The first region should contain
the address and the length of the shared message interrupt register set.
The second region should contain the address of aliased MSIIR register for
platforms that have such an alias.
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
......
Documentation/powerpc/firmware-assisted-dump.txt 0 → 100644
View file @ 5375871d
This diff is collapsed.
Documentation/powerpc/mpc52xx.txt
View file @ 5375871d
......@@ -2,7 +2,7 @@ Linux 2.6.x on MPC52xx family
-----------------------------
For the latest info, go to http://www.246tNt.com/mpc52xx/
To compile/use :
- U-Boot:
......@@ -10,23 +10,23 @@ To compile/use :
if you wish to ).
# make lite5200_defconfig
# make uImage
then, on U-boot:
=> tftpboot 200000 uImage
=> tftpboot 400000 pRamdisk
=> bootm 200000 400000
- DBug:
# <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION
if you wish to ).
# make lite5200_defconfig
# cp your_initrd.gz arch/ppc/boot/images/ramdisk.image.gz
# make zImage.initrd
# make
# make zImage.initrd
# make
then in DBug:
DBug> dn -i zImage.initrd.lite5200
Some remarks :
- The port is named mpc52xxx, and config options are PPC_MPC52xx. The MGT5100
......
Documentation/powerpc/phyp-assisted-dump.txt deleted 100644 → 0
View file @ b57cb723
Hypervisor-Assisted Dump
------------------------
November 2007
The goal of hypervisor-assisted dump is to enable the dump of
a crashed system, and to do so from a fully-reset system, and
to minimize the total elapsed time until the system is back
in production use.
As compared to kdump or other strategies, hypervisor-assisted
dump offers several strong, practical advantages:
-- Unlike kdump, the system has been reset, and loaded
with a fresh copy of the kernel. In particular,
PCI and I/O devices have been reinitialized and are
in a clean, consistent state.
-- As the dump is performed, the dumped memory becomes
immediately available to the system for normal use.
-- After the dump is completed, no further reboots are
required; the system will be fully usable, and running
in its normal, production mode on its normal kernel.
The above can only be accomplished by coordination with,
and assistance from the hypervisor. The procedure is
as follows:
-- When a system crashes, the hypervisor will save
the low 256MB of RAM to a previously registered
save region. It will also save system state, system
registers, and hardware PTE's.
-- After the low 256MB area has been saved, the
hypervisor will reset PCI and other hardware state.
It will *not* clear RAM. It will then launch the
bootloader, as normal.
-- The freshly booted kernel will notice that there
is a new node (ibm,dump-kernel) in the device tree,
indicating that there is crash data available from
a previous boot. It will boot into only 256MB of RAM,
reserving the rest of system memory.
-- Userspace tools will parse /sys/kernel/release_region
and read /proc/vmcore to obtain the contents of memory,
which holds the previous crashed kernel. The userspace
tools may copy this info to disk, or network, nas, san,
iscsi, etc. as desired.
For Example: the values in /sys/kernel/release-region
would look something like this (address-range pairs).
CPU:0x177fee000-0x10000: HPTE:0x177ffe020-0x1000: /
DUMP:0x177fff020-0x10000000, 0x10000000-0x16F1D370A
-- As the userspace tools complete saving a portion of
dump, they echo an offset and size to
/sys/kernel/release_region to release the reserved
memory back to general use.
An example of this is:
"echo 0x40000000 0x10000000 > /sys/kernel/release_region"
which will release 256MB at the 1GB boundary.
Please note that the hypervisor-assisted dump feature
is only available on Power6-based systems with recent
firmware versions.
Implementation details:
----------------------
During boot, a check is made to see if firmware supports
this feature on this particular machine. If it does, then
we check to see if a active dump is waiting for us. If yes
then everything but 256 MB of RAM is reserved during early
boot. This area is released once we collect a dump from user
land scripts that are run. If there is dump data, then
the /sys/kernel/release_region file is created, and
the reserved memory is held.
If there is no waiting dump data, then only the highest
256MB of the ram is reserved as a scratch area. This area
is *not* released: this region will be kept permanently
reserved, so that it can act as a receptacle for a copy
of the low 256MB in the case a crash does occur. See,
however, "open issues" below, as to whether
such a reserved region is really needed.
Currently the dump will be copied from /proc/vmcore to a
a new file upon user intervention. The starting address
to be read and the range for each data point in provided
in /sys/kernel/release_region.
The tools to examine the dump will be same as the ones
used for kdump.
General notes:
--------------
Security: please note that there are potential security issues
with any sort of dump mechanism. In particular, plaintext
(unencrypted) data, and possibly passwords, may be present in
the dump data. Userspace tools must take adequate precautions to
preserve security.
Open issues/ToDo:
------------
o The various code paths that tell the hypervisor that a crash
occurred, vs. it simply being a normal reboot, should be
reviewed, and possibly clarified/fixed.
o Instead of using /sys/kernel, should there be a /sys/dump
instead? There is a dump_subsys being created by the s390 code,
perhaps the pseries code should use a similar layout as well.
o Is reserving a 256MB region really required? The goal of
reserving a 256MB scratch area is to make sure that no
important crash data is clobbered when the hypervisor
save low mem to the scratch area. But, if one could assure
that nothing important is located in some 256MB area, then
it would not need to be reserved. Something that can be
improved in subsequent versions.
o Still working the kdump team to integrate this with kdump,
some work remains but this would not affect the current
patches.
o Still need to write a shell script, to copy the dump away.
Currently I am parsing it manually.
MAINTAINERS
View file @ 5375871d
......@@ -4071,7 +4071,7 @@ M: Josh Boyer <jwboyer@gmail.com>
M: Matt Porter <mporter@kernel.crashing.org>
W: http://www.penguinppc.org/
L: linuxppc-dev@lists.ozlabs.org
T: git git://git.infradead.org/users/jwboyer/powerpc-4xx.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
F: arch/powerpc/platforms/40x/
F: arch/powerpc/platforms/44x/
......
arch/powerpc/Kconfig
View file @ 5375871d
......@@ -134,6 +134,7 @@ config PPC
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
select SPARSE_IRQ
select IRQ_PER_CPU
select IRQ_DOMAIN
select GENERIC_IRQ_SHOW
......@@ -377,13 +378,16 @@ config CRASH_DUMP
The same kernel binary can be used as production kernel and dump
capture kernel.
config PHYP_DUMP
bool "Hypervisor-assisted dump (EXPERIMENTAL)"
depends on PPC_PSERIES && EXPERIMENTAL
config FA_DUMP
bool "Firmware-assisted dump"
depends on PPC64 && PPC_RTAS && CRASH_DUMP
help
Hypervisor-assisted dump is meant to be a kdump replacement
offering robustness and speed not possible without system
hypervisor assistance.
A robust mechanism to get reliable kernel crash dump with
assistance from firmware. This approach does not use kexec,
instead firmware assists in booting the kdump kernel
while preserving memory contents. Firmware-assisted dump
is meant to be a kdump replacement offering robustness and
speed not possible without system firmware assistance.
If unsure, say "N"
......@@ -612,7 +616,7 @@ endmenu
config ISA_DMA_API
bool
default !PPC_ISERIES || PCI
default PCI
menu "Bus options"
......
arch/powerpc/Kconfig.debug
View file @ 5375871d
......@@ -196,13 +196,6 @@ config PPC_EARLY_DEBUG_MAPLE
help
Select this to enable early debugging for Maple.
config PPC_EARLY_DEBUG_ISERIES
bool "iSeries HV Console"
depends on PPC_ISERIES
help
Select this to enable early debugging for legacy iSeries. You need
to hit "Ctrl-x Ctrl-x" to see the messages on the console.
config PPC_EARLY_DEBUG_PAS_REALMODE
bool "PA Semi real mode"
depends on PPC_PASEMI
......
arch/powerpc/Makefile
View file @ 5375871d
......@@ -157,6 +157,7 @@ core-y += arch/powerpc/kernel/ \
arch/powerpc/net/
core-$(CONFIG_XMON) += arch/powerpc/xmon/
core-$(CONFIG_KVM) += arch/powerpc/kvm/
core-$(CONFIG_PERF_EVENTS) += arch/powerpc/perf/
drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/
......
arch/powerpc/boot/Makefile
View file @ 5375871d
......@@ -184,7 +184,6 @@ image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800
image-$(CONFIG_PPC_ISERIES) += zImage.iseries
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
......@@ -247,7 +246,7 @@ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
cuImage.mpc8548cds \
cuImage.mpc8548cds_32b \
cuImage.mpc8555cds
image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
......@@ -311,12 +310,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
# The iseries hypervisor won't take an ET_DYN executable, so this
# changes the type (byte 17) in the file to ET_EXEC (2).
$(obj)/zImage.iseries: vmlinux
$(STRIP) -s -R .comment $< -o $@
printf "\x02" | dd of=$@ conv=notrunc bs=1 seek=17
$(obj)/uImage: vmlinux $(wrapperbits)
$(call if_changed,wrap,uboot)
......@@ -364,7 +357,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
# anything not in $(targets)
clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
zImage.iseries zImage.miboot zImage.pmac zImage.pseries \
zImage.miboot zImage.pmac zImage.pseries \
zImage.maple simpleImage.* otheros.bld *.dtb
# clean up files cached by wrapper
......
arch/powerpc/boot/dts/a4m072.dts 0 → 100644
View file @ 5375871d
/*
* a4m072 board Device Tree Source
*
* Copyright (C) 2011 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* Copyright (C) 2007 Semihalf
* Marian Balakowicz <m8@semihalf.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "mpc5200b.dtsi"
/ {
model = "anonymous,a4m072";
compatible = "anonymous,a4m072";
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; /* From boot loader */
system-frequency = <0>; /* From boot loader */
cdm@200 {
fsl,init-ext-48mhz-en = <0x0>;
fsl,init-fd-enable = <0x01>;
fsl,init-fd-counters = <0x3333>;
};
timer@600 {
fsl,has-wdt;
};
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
gpio-controller;
#gpio-cells = <2>;
};
spi@f00 {
status = "disabled";
};
psc@2000 {
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
};
psc@2200 {
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2200 0x100>;
interrupts = <2 2 0>;
};
psc@2400 {
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2400 0x100>;
interrupts = <2 3 0>;
};
psc@2600 {
status = "disabled";
};
psc@2800 {
status = "disabled";
};
psc@2c00 {
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
ethernet@3000 {
phy-handle = <&phy0>;
};
mdio@3000 {
phy0: ethernet-phy@1f {
reg = <0x1f>;
interrupts = <1 2 0>; /* IRQ 2 active low */
};
};
i2c@3d00 {
status = "disabled";
};
i2c@3d40 {
hwmon@2e {
compatible = "nsc,lm87";
reg = <0x2e>;
};
rtc@51 {
compatible = "nxp,rtc8564";
reg = <0x51>;
};
};
};
localbus {
compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xfe000000 0x02000000
1 0 0x62000000 0x00400000
2 0 0x64000000 0x00200000
3 0 0x66000000 0x01000000
6 0 0x68000000 0x01000000
7 0 0x6a000000 0x00000004>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
bank-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
};
sram0@1,0 {
compatible = "mtd-ram";
reg = <1 0x00000 0x00400000>;
bank-width = <2>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x16 */
0xc000 0 0 1 &mpc5200_pic 1 3 3
0xc000 0 0 2 &mpc5200_pic 1 3 3
0xc000 0 0 3 &mpc5200_pic 1 3 3
0xc000 0 0 4 &mpc5200_pic 1 3 3>;
clock-frequency = <0>; /* From boot loader */
interrupts = <2 8 0 2 9 0 2 10 0>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
};
};
arch/powerpc/boot/dts/bluestone.dts
View file @ 5375871d
......@@ -33,7 +33,7 @@ / {
aliases {
ethernet0 = &EMAC0;
serial0 = &UART0;
//serial1 = &UART1; --gcl missing UART1 label
serial1 = &UART1;
};
cpus {
......@@ -52,7 +52,7 @@ cpu@0 {
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
//next-level-cache = <&L2C0>; --gcl missing L2C0 label
next-level-cache = <&L2C0>;
};
};
......@@ -117,6 +117,16 @@ CPR0: cpr {
dcr-reg = <0x00c 0x002>;
};
L2C0: l2c {
compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
dcr-reg = <0x020 0x008
0x030 0x008>;
cache-line-size = <32>;
cache-size = <262144>;
interrupt-parent = <&UIC1>;
interrupts = <11 1>;
};
plb {
compatible = "ibm,plb4";
#address-cells = <2>;
......@@ -182,6 +192,53 @@ partition@1a0000 {
reg = <0x001a0000 0x00060000>;
};
};
ndfc@1,0 {
compatible = "ibm,ndfc";
reg = <0x00000003 0x00000000 0x00002000>;
ccr = <0x00001000>;
bank-settings = <0x80002222>;
#address-cells = <1>;
#size-cells = <1>;
/* 2Gb Nand Flash */
nand {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x00000000 0x00C00000>;
};
partition@c00000 {
label = "environment";
reg = <0x00C00000 0x00B00000>;
};
partition@1700000 {
label = "kernel";
reg = <0x01700000 0x00E00000>;
};
partition@2500000 {
label = "root";
reg = <0x02500000 0x08200000>;
};
partition@a700000 {
label = "device-tree";
reg = <0x0A700000 0x00B00000>;
};
partition@b200000 {
label = "config";
reg = <0x0B200000 0x00D00000>;
};
partition@bf00000 {
label = "diag";
reg = <0x0BF00000 0x00C00000>;
};
partition@cb00000 {
label = "vendor";
reg = <0x0CB00000 0x3500000>;
};
};
};
};
UART0: serial@ef600300 {
......@@ -195,11 +252,36 @@ UART0: serial@ef600300 {
interrupts = <0x1 0x4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600400 0x00000008>;
virtual-reg = <0xef600400>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC0>;
interrupts = <0x1 0x4>;
};
IIC0: i2c@ef600700 {
compatible = "ibm,iic";
reg = <0xef600700 0x00000014>;
interrupt-parent = <&UIC0>;
interrupts = <0x2 0x4>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "stm,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC0>;
interrupts = <0x9 0x8>;
};
sttm@4C {
compatible = "adm,adm1032";
reg = <0x4C>;
interrupt-parent = <&UIC1>;
interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
};
};
IIC1: i2c@ef600800 {
......@@ -250,5 +332,46 @@ EMAC0: ethernet@ef600c00 {
};
};
PCIE0: pciex@d00000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
primary;
port = <0x0>; /* port number */
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
0x0000000c 0x08010000 0x00001000>; /* Registers */
dcr-reg = <0x100 0x020>;
sdr-base = <0x300>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 40 to 0x7f */
bus-range = <0x40 0x7f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
};
};
};
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
View file @ 5375871d
......@@ -202,7 +202,7 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-etsec1-timer-0.dtsi"
usb@22000 {
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
reg = <0x22000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -210,7 +210,7 @@ usb@22000 {
};
usb@23000 {
compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
......
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
View file @ 5375871d
......@@ -89,6 +89,21 @@ pcie@0 {
};
};
&rio {
compatible = "fsl,srio";
interrupts = <48 2 0 0>;
#address-cells = <2>;
#size-cells = <2>;
fsl,srio-rmu-handle = <&rmu>;
ranges;
port1 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <1>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -134,6 +149,7 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-sec2.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-rmu-0.dtsi"
global-utilities@e0000 {
compatible = "fsl,mpc8548-guts";
......
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
View file @ 5375871d
......@@ -43,7 +43,9 @@ aliases {
serial0 = &serial0;
serial1 = &serial1;
ethernet0 = &enet0;
ethernet1 = &enet2;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
......
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
View file @ 5375871d
......@@ -156,6 +156,9 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
compatible = "fsl,p1010-esdhc", "fsl,esdhc";
......
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
View file @ 5375871d
......@@ -142,7 +142,13 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-usb2-dr-1.dtsi"
usb@23000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
......
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
View file @ 5375871d
......@@ -142,8 +142,15 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
sdhci,auto-cmd12;
};
/include/ "pq3-sec3.3-0.dtsi"
/include/ "pq3-mpic.dtsi"
......
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
View file @ 5375871d
......@@ -35,7 +35,11 @@
&lbc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
/*
* The localbus on the P1022 is not a simple-bus because of the eLBC
* pin muxing when the DIU is enabled.
*/
compatible = "fsl,p1022-elbc", "fsl,elbc";
interrupts = <19 2 0 0>;
};
......@@ -199,7 +203,13 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-usb2-dr-1.dtsi"
usb@23000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
......
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
View file @ 5375871d
......@@ -142,6 +142,9 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
crypto: crypto@300000 {
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
......
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
View file @ 5375871d
......@@ -171,6 +171,9 @@ L2: l2-cache-controller@20000 {
/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
usb@22000 {
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
};
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-timer-0.dtsi"
......
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
View file @ 5375871d
......@@ -309,12 +309,14 @@ sdhc@114000 {
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 {
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
phy_type = "utmi";
port0;
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 {
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
dr_mode = "host";
phy_type = "utmi";
};
......
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
View file @ 5375871d
......@@ -336,12 +336,14 @@ sdhc@114000 {
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 {
compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
phy_type = "utmi";
port0;
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 {
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
dr_mode = "host";
phy_type = "utmi";
};
......
arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
View file @ 5375871d
......@@ -291,6 +291,12 @@ spi@110000 {
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb@210000 {
compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb@211000 {
compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
};
/include/ "qoriq-sec4.1-0.dtsi"
};
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
View file @ 5375871d
......@@ -339,12 +339,14 @@ sdhc@114000 {
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
usb0: usb@210000 {
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
phy_type = "utmi";
port0;
};
/include/ "qoriq-usb2-dr-0.dtsi"
usb1: usb@211000 {
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
dr_mode = "host";
phy_type = "utmi";
};
......
arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
View file @ 5375871d
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,7 @@ ethernet@24000 {
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
......
arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
View file @ 5375871d
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,7 @@ ethernet@25000 {
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
......
arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
View file @ 5375871d
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,7 @@ ethernet@26000 {
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
};
......
arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
View file @ 5375871d
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2011-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,7 @@ ethernet@27000 {
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
};
......
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
View file @ 5375871d
......@@ -39,6 +39,9 @@ mpic: pic@40000 {
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
timer@41100 {
......
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
View file @ 5375871d
......@@ -33,32 +33,32 @@
*/
crypto@30000 {
compatible = "fsl,sec4.4", "fsl,sec4.0";
compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30000 0x10000>;
interrupts = <58 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <45 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <45 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <45 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <45 2 0 0>;
};
......
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
View file @ 5375871d
......@@ -53,7 +53,7 @@ timer@41100 {
msi0: msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x200>;
reg = <0x41600 0x200 0x44140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0 0 0
......@@ -68,7 +68,7 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = "fsl,mpic-msi";
reg = <0x41800 0x200>;
reg = <0x41800 0x200 0x45140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe8 0 0 0
......@@ -83,7 +83,7 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = "fsl,mpic-msi";
reg = <0x41a00 0x200>;
reg = <0x41a00 0x200 0x46140 4>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xf0 0 0 0
......
arch/powerpc/boot/dts/ge_imp3a.dts 0 → 100644
View file @ 5375871d
/*
* GE IMP3A Device Tree Source
*
* Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Based on: P2020 DS Device Tree Source
* Copyright 2009 Freescale Semiconductor Inc.
*/
/include/ "fsl/p2020si-pre.dtsi"
/ {
model = "GE_IMP3A";
compatible = "ge,imp3a";
memory {
device_type = "memory";
};
lbc: localbus@fef05000 {
reg = <0 0xfef05000 0 0x1000>;
ranges = <0x0 0x0 0x0 0xff000000 0x01000000
0x1 0x0 0x0 0xe0000000 0x08000000
0x2 0x0 0x0 0xe8000000 0x08000000
0x3 0x0 0x0 0xfc100000 0x00020000
0x4 0x0 0x0 0xfc000000 0x00008000
0x5 0x0 0x0 0xfc008000 0x00008000
0x6 0x0 0x0 0xfee00000 0x00040000
0x7 0x0 0x0 0xfee80000 0x00040000>;
/* nor@0,0 is a mirror of part of the memory in nor@1,0
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x1000000>;
read-only;
};
};
*/
nor@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ge,imp3a-paged-flash", "cfi-flash";
reg = <0x1 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "user";
reg = <0x0 0x7800000>;
};
partition@7800000 {
label = "firmware";
reg = <0x7800000 0x800000>;
read-only;
};
};
nvram@3,0 {
device_type = "nvram";
compatible = "simtek,stk14ca8";
reg = <0x3 0x0 0x20000>;
};
fpga@4,0 {
compatible = "ge,imp3a-fpga-regs";
reg = <0x4 0x0 0x20>;
};
gef_pic: pic@4,20 {
#interrupt-cells = <1>;
interrupt-controller;
device_type = "interrupt-controller";
compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
reg = <0x4 0x20 0x20>;
interrupts = <6 7 0 0>;
};
gef_gpio: gpio@4,400 {
#gpio-cells = <2>;
compatible = "ge,imp3a-gpio";
reg = <0x4 0x400 0x24>;
gpio-controller;
};
wdt@4,800 {
compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
"gef,fpga-wdt";
reg = <0x4 0x800 0x8>;
interrupts = <10 4>;
interrupt-parent = <&gef_pic>;
};
/* Second watchdog available, driver currently supports one.
wdt@4,808 {
compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
"gef,fpga-wdt";
reg = <0x4 0x808 0x8>;
interrupts = <9 4>;
interrupt-parent = <&gef_pic>;
};
*/
nand@6,0 {
compatible = "fsl,elbc-fcm-nand";
reg = <0x6 0x0 0x40000>;
};
nand@7,0 {
compatible = "fsl,elbc-fcm-nand";
reg = <0x7 0x0 0x40000>;
};
};
soc: soc@fef00000 {
ranges = <0x0 0 0xfef00000 0x100000>;
i2c@3000 {
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
};
hwmon@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
rtc@51 {
compatible = "epson,rx8581";
reg = <0x51>;
};
eti@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
};
usb@22000 {
phy_type = "ulpi";
dr_mode = "host";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0xc 0x4>;
reg = <0x1>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&gef_pic>;
interrupts = <0xb 0x4>;
reg = <0x2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26520 {
status = "disabled";
};
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "gmii";
};
enet2: ethernet@26000 {
status = "disabled";
};
};
pci0: pcie@fef08000 {
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
reg = <0 0xfef08000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
pci1: pcie@fef09000 {
reg = <0 0xfef09000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
pci2: pcie@fef0a000 {
reg = <0 0xfef0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
};
/include/ "fsl/p2020si-post.dtsi"
arch/powerpc/boot/dts/mpc836x_mds.dts
View file @ 5375871d
......@@ -405,6 +405,10 @@ phy1: ethernet-phy@01 {
reg = <0x1>;
device_type = "ethernet-phy";
};
tbi-phy@2 {
device_type = "tbi-phy";
reg = <0x2>;
};
};
qeic: interrupt-controller@80 {
......
arch/powerpc/boot/dts/mpc8536ds.dts
View file @ 5375871d
/*
* MPC8536 DS Device Tree Source
*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -34,6 +34,10 @@ memory {
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
0x2 0x0 0x0 0xffa00000 0x00040000
0x3 0x0 0x0 0xffdf0000 0x00008000>;
};
board_soc: soc: soc@ffe00000 {
......
arch/powerpc/boot/dts/mpc8536ds.dtsi
View file @ 5375871d
......@@ -32,6 +32,99 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x03000000>;
label = "ramdisk-nor";
};
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
partition@4000000 {
reg = <0x04000000 0x00400000>;
label = "kernel-nor";
};
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "fs-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00080000>;
label = "dtb-nor";
};
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8536-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "fs-nand";
};
partition@12000000 {
reg = <0x12000000 0x08000000>;
label = "ramdisk-nand";
};
partition@1a000000 {
reg = <0x1a000000 0x04000000>;
label = "kernel-nand";
};
partition@1e000000 {
reg = <0x1e000000 0x01000000>;
label = "dtb-nand";
};
partition@1f000000 {
reg = <0x1f000000 0x21000000>;
label = "empty-nand";
};
};
board-control@3,0 {
compatible = "fsl,mpc8536ds-fpga-pixis";
reg = <0x3 0x0 0x8000>;
};
};
&board_soc {
i2c@3100 {
rtc@68 {
......
arch/powerpc/boot/dts/mpc8536ds_36b.dts
View file @ 5375871d
/*
* MPC8536DS Device Tree Source (36-bit address map)
*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2009, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -33,7 +33,11 @@ memory {
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
reg = <0xf 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x2 0x0 0xf 0xffa00000 0x00040000
0x3 0x0 0xf 0xffdf0000 0x00008000>;
};
board_soc: soc: soc@fffe00000 {
......
arch/powerpc/boot/dts/mpc8548cds.dts deleted 100644 → 0
View file @ b57cb723
/*
* MPC8548 CDS Device Tree Source
*
* Copyright 2006, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "fsl/mpc8548si-pre.dtsi"
/ {
model = "MPC8548CDS";
compatible = "MPC8548CDS", "MPC85xxCDS";
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
memory {
device_type = "memory";
reg = <0 0 0x0 0x8000000>; // 128M at 0x0
};
lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
};
soc: soc8548@e0000000 {
ranges = <0 0x0 0xe0000000 0x100000>;
i2c@3000 {
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
i2c@3100 {
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <5 1 0 0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupts = <5 1 0 0>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupts = <5 1 0 0>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupts = <5 1 0 0>;
reg = <0x3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet2: ethernet@26000 {
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
};
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet3: ethernet@27000 {
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
};
mdio@27520 {
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
pci0: pci@e0008000 {
reg = <0 0xe0008000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x5 (PCIX Slot 3) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
/* IDSEL 0x6 (PCIX Slot 4) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDSEL 0x8 (PCIX Slot 5) */
0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0xC (Tsi310 bridge) */
0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x14 (Slot 2) */
0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x15 (Slot 3) */
0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
/* IDSEL 0x16 (Slot 4) */
0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDSEL 0x18 (Slot 5) */
0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
pci_bridge@1c {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x04 (VIA chip) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x05 (8139) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
/* IDSEL 0x06 (Slot 6) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDESL 0x07 (Slot 7) */
0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x80000>;
clock-frequency = <33333333>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0x2000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1 0 0>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
};
};
};
pci1: pci@e0009000 {
reg = <0 0xe0009000 0 0x1000>;
ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
};
pci2: pcie@e000a000 {
reg = <0 0xe000a000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/mpc8548si-post.dtsi"
arch/powerpc/boot/dts/mpc8548cds.dtsi 0 → 100644
View file @ 5375871d
/*
* MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&board_lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x01000000>;
bank-width = <2>;
device-width = <2>;
partition@0 {
reg = <0x0 0x0b00000>;
label = "ramdisk-nor";
};
partition@300000 {
reg = <0x0b00000 0x0400000>;
label = "kernel-nor";
};
partition@700000 {
reg = <0x0f00000 0x060000>;
label = "dtb-nor";
};
partition@760000 {
reg = <0x0f60000 0x020000>;
label = "env-nor";
read-only;
};
partition@780000 {
reg = <0x0f80000 0x080000>;
label = "u-boot-nor";
read-only;
};
};
board-control@1,0 {
compatible = "fsl,mpc8548cds-fpga";
reg = <0x1 0x0 0x1000>;
};
};
&board_soc {
i2c@3000 {
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
i2c@3100 {
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <5 1 0 0>;
reg = <0x0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupts = <5 1 0 0>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupts = <5 1 0 0>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupts = <5 1 0 0>;
reg = <0x3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet2: ethernet@26000 {
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
};
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet3: ethernet@27000 {
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
};
mdio@27520 {
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
&board_pci0 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x5 (PCIX Slot 3) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
/* IDSEL 0x6 (PCIX Slot 4) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDSEL 0x8 (PCIX Slot 5) */
0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0xC (Tsi310 bridge) */
0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x14 (Slot 2) */
0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x15 (Slot 3) */
0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
/* IDSEL 0x16 (Slot 4) */
0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDSEL 0x18 (Slot 5) */
0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
pci_bridge@1c {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x04 (VIA chip) */
0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
/* IDSEL 0x05 (8139) */
0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
/* IDSEL 0x06 (Slot 6) */
0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
/* IDESL 0x07 (Slot 7) */
0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x80000>;
clock-frequency = <33333333>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0x2000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
interrupt-controller;
device_type = "interrupt-controller";
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <0 1 0 0>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
};
};
};
arch/powerpc/boot/dts/mpc8548cds_32b.dts 0 → 100644
View file @ 5375871d
/*
* MPC8548 CDS Device Tree Source (32-bit address map)
*
* Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "fsl/mpc8548si-pre.dtsi"
/ {
model = "MPC8548CDS";
compatible = "MPC8548CDS", "MPC85xxCDS";
memory {
device_type = "memory";
reg = <0 0 0x0 0x8000000>; // 128M at 0x0
};
board_lbc: lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
ranges = <0x0 0x0 0x0 0xff000000 0x01000000
0x1 0x0 0x0 0xf8004000 0x00001000>;
};
board_soc: soc: soc8548@e0000000 {
ranges = <0 0x0 0xe0000000 0x100000>;
};
board_pci0: pci0: pci@e0008000 {
reg = <0 0xe0008000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
};
pci1: pci@e0009000 {
reg = <0 0xe0009000 0 0x1000>;
ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
};
pci2: pcie@e000a000 {
reg = <0 0xe000a000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
rio: rapidio@e00c0000 {
reg = <0x0 0xe00c0000 0x0 0x20000>;
port1 {
ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
};
};
};
/*
* mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
* for interrupt-map & interrupt-map-mask.
*/
/include/ "fsl/mpc8548si-post.dtsi"
/include/ "mpc8548cds.dtsi"
arch/powerpc/boot/dts/mpc8548cds_36b.dts 0 → 100644
View file @ 5375871d
/*
* MPC8548 CDS Device Tree Source (36-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "fsl/mpc8548si-pre.dtsi"
/ {
model = "MPC8548CDS";
compatible = "MPC8548CDS", "MPC85xxCDS";
memory {
device_type = "memory";
reg = <0 0 0x0 0x8000000>; // 128M at 0x0
};
board_lbc: lbc: localbus@fe0005000 {
reg = <0xf 0xe0005000 0 0x1000>;
ranges = <0x0 0x0 0xf 0xff000000 0x01000000
0x1 0x0 0xf 0xf8004000 0x00001000>;
};
board_soc: soc: soc8548@fe0000000 {
ranges = <0 0xf 0xe0000000 0x100000>;
};
board_pci0: pci0: pci@fe0008000 {
reg = <0xf 0xe0008000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
};
pci1: pci@fe0009000 {
reg = <0xf 0xe0009000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
};
pci2: pcie@fe000a000 {
reg = <0xf 0xe000a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
rio: rapidio@fe00c0000 {
reg = <0xf 0xe00c0000 0x0 0x20000>;
port1 {
ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;
};
};
};
/*
* mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
* for interrupt-map & interrupt-map-mask.
*/
/include/ "fsl/mpc8548si-post.dtsi"
/include/ "mpc8548cds.dtsi"
arch/powerpc/boot/dts/mpc8572ds.dtsi
View file @ 5375871d
......@@ -41,37 +41,47 @@ nor@0,0 {
bank-width = <2>;
device-width = <1>;
ramdisk@0 {
partition@0 {
reg = <0x0 0x03000000>;
read-only;
label = "ramdisk-nor";
};
diagnostic@3000000 {
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
dink@3e00000 {
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
kernel@4000000 {
partition@4000000 {
reg = <0x04000000 0x00400000>;
read-only;
label = "kernel-nor";
};
jffs2@4400000 {
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "fs-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00060000>;
label = "dtb-nor";
};
dtb@7f00000 {
reg = <0x07f00000 0x00080000>;
partition@7f60000 {
reg = <0x07f60000 0x00020000>;
label = "env-nor";
read-only;
};
u-boot@7f80000 {
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
......@@ -83,31 +93,35 @@ nand@2,0 {
"fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
u-boot@0 {
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
jffs2@2000000 {
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "fs-nand";
};
ramdisk@12000000 {
partition@12000000 {
reg = <0x12000000 0x08000000>;
read-only;
label = "ramdisk-nand";
};
kernel@1a000000 {
partition@1a000000 {
reg = <0x1a000000 0x04000000>;
label = "kernel-nand";
};
dtb@1e000000 {
partition@1e000000 {
reg = <0x1e000000 0x01000000>;
read-only;
label = "dtb-nand";
};
empty@1f000000 {
partition@1f000000 {
reg = <0x1f000000 0x21000000>;
label = "empty-nand";
};
};
......
arch/powerpc/boot/dts/p1010rdb.dtsi
View file @ 5375871d
......@@ -138,7 +138,7 @@ flash@0 {
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <50000000>;
spi-max-frequency = <40000000>;
partition@0 {
/* 1MB for u-boot Bootloader Image */
......@@ -196,7 +196,7 @@ phy2: ethernet-phy@2 {
};
tbi-phy@3 {
device-type = "tbi-phy";
device_type = "tbi-phy";
reg = <0x3>;
};
};
......
arch/powerpc/boot/dts/p1020rdb-pc.dtsi 0 → 100644
View file @ 5375871d
/*
* P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* This location must not be altered */
/* 256KB for Vitesse 7385 Switch firmware */
reg = <0x0 0x00040000>;
label = "NOR Vitesse-7385 Firmware";
read-only;
};
partition@40000 {
/* 256KB for DTB Image */
reg = <0x00040000 0x00040000>;
label = "NOR DTB Image";
};
partition@80000 {
/* 3.5 MB for Linux Kernel Image */
reg = <0x00080000 0x00380000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 11MB for JFFS2 based Root file System */
reg = <0x00400000 0x00b00000>;
label = "NOR JFFS2 Root File System";
};
partition@f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x00f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1020-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 4MB for Linux Kernel Image */
reg = <0x00200000 0x00400000>;
label = "NAND Linux Kernel Image";
};
partition@600000 {
/* 4MB for Compressed Root file System Image */
reg = <0x00600000 0x00400000>;
label = "NAND Compressed RFS Image";
};
partition@a00000 {
/* 7MB for JFFS2 based Root file System */
reg = <0x00a00000 0x00700000>;
label = "NAND JFFS2 Root File System";
};
partition@1100000 {
/* 15MB for JFFS2 based Root file System */
reg = <0x01100000 0x00f00000>;
label = "NAND Writable User area";
};
};
L2switch@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cpld";
reg = <0x3 0x0 0x20000>;
read-only;
};
};
&soc {
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "u-boot";
read-only;
};
partition@dtb {
/* 512KB for DTB Image*/
reg = <0x00080000 0x00080000>;
label = "dtb";
};
partition@kernel {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "kernel";
};
partition@fs {
/* 4MB for Compressed RFS Image */
reg = <0x00500000 0x00400000>;
label = "file system";
};
partition@jffs-fs {
/* 7MB for JFFS2 based RFS */
reg = <0x00900000 0x00700000>;
label = "file system jffs2";
};
};
};
usb@22000 {
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
phy_type = "ulpi";
};
*/
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
device_type = "tbi-phy";
reg = <0x11>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
arch/powerpc/boot/dts/p1020rdb-pc_32b.dts 0 → 100644
View file @ 5375871d
/*
* P1020 RDB-PC Device Tree Source (32-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000
0x3 0x0 0x0 0xffa00000 0x00020000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
arch/powerpc/boot/dts/p1020rdb-pc_36b.dts 0 → 100644
View file @ 5375871d
/*
* P1020 RDB-PC Device Tree Source (36-bit address map)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1020si-pre.dtsi"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0xf 0xef000000 0x01000000
0x1 0x0 0xf 0xff800000 0x00040000
0x2 0x0 0xf 0xffb00000 0x00040000
0x3 0x0 0xf 0xffa00000 0x00020000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "fsl/p1020si-post.dtsi"
arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts 0 → 100644
View file @ 5375871d
/*
* P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
* eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
*
* Please note to add "-b 0" for core0's dts compiling.
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020rdb-pc_32b.dts"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
aliases {
ethernet1 = &enet1;
ethernet2 = &enet2;
serial0 = &serial0;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
PowerPC,P1020@1 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
serial1: serial@4600 {
status = "disabled";
};
enet0: ethernet@b0000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
42 29 30 34 /* serial1, enet0-queue-group0 */
17 18 24 45 /* enet0-queue-group1, crypto */
>;
pic-no-reset;
};
};
};
arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts 0 → 100644
View file @ 5375871d
/*
* P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
*
* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
* can be shared, all the other devices must be assigned to one core only.
* This dts allows core1 to have l2, eth0, crypto.
*
* Please note to add "-b 1" for core1's dts compiling.
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "p1020rdb-pc_32b.dts"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
aliases {
ethernet0 = &enet0;
serial0 = &serial1;
};
cpus {
PowerPC,P1020@0 {
status = "disabled";
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
status = "disabled";
};
soc@ffe00000 {
ecm-law@0 {
status = "disabled";
};
ecm@1000 {
status = "disabled";
};
memory-controller@2000 {
status = "disabled";
};
i2c@3000 {
status = "disabled";
};
i2c@3100 {
status = "disabled";
};
serial0: serial@4500 {
status = "disabled";
};
spi@7000 {
status = "disabled";
};
gpio: gpio-controller@f000 {
status = "disabled";
};
dma@21300 {
status = "disabled";
};
mdio@24000 {
status = "disabled";
};
mdio@25000 {
status = "disabled";
};
enet1: ethernet@b1000 {
status = "disabled";
};
enet2: ethernet@b2000 {
status = "disabled";
};
usb@22000 {
status = "disabled";
};
sdhci@2e000 {
status = "disabled";
};
mpic: pic@40000 {
protected-sources = <
16 /* ecm, mem, L2, pci0, pci1 */
43 42 59 /* i2c, serial0, spi */
47 63 62 /* gpio, tdm */
20 21 22 23 /* dma */
03 02 /* mdio */
35 36 40 /* enet1-queue-group0 */
51 52 67 /* enet1-queue-group1 */
31 32 33 /* enet2-queue-group0 */
25 26 27 /* enet2-queue-group1 */
28 72 58 /* usb, sdhci, crypto */
0xb0 0xb1 0xb2 /* message */
0xb3 0xb4 0xb5
0xb6 0xb7
0xe0 0xe1 0xe2 /* msi */
0xe3 0xe4 0xe5
0xe6 0xe7 /* sdhci, crypto , pci */
>;
pic-no-reset;
};
msi@41600 {
status = "disabled";
};
global-utilities@e0000 { //global utilities block
status = "disabled";
};
};
pci0: pcie@ffe09000 {
status = "disabled";
};
pci1: pcie@ffe0a000 {
status = "disabled";
};
};
arch/powerpc/boot/dts/p1021rdb.dts 0 → 100644
View file @ 5375871d
/*
* P1021 RDB Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1021si-pre.dtsi"
/ {
model = "fsl,P1021RDB";
compatible = "fsl,P1021RDB-PC";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
qe: qe@ffe80000 {
ranges = <0x0 0x0 0xffe80000 0x40000>;
reg = <0 0xffe80000 0 0x480>;
brg-frequency = <0>;
bus-frequency = <0>;
};
};
/include/ "p1021rdb.dtsi"
/include/ "fsl/p1021si-post.dtsi"
arch/powerpc/boot/dts/p1021rdb.dtsi 0 → 100644
View file @ 5375871d
/*
* P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* This location must not be altered */
/* 256KB for Vitesse 7385 Switch firmware */
reg = <0x0 0x00040000>;
label = "NOR Vitesse-7385 Firmware";
read-only;
};
partition@40000 {
/* 256KB for DTB Image */
reg = <0x00040000 0x00040000>;
label = "NOR DTB Image";
};
partition@80000 {
/* 3.5 MB for Linux Kernel Image */
reg = <0x00080000 0x00380000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 11MB for JFFS2 based Root file System */
reg = <0x00400000 0x00b00000>;
label = "NOR JFFS2 Root File System";
};
partition@f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x00f00000 0x00100000>;
label = "NOR U-Boot Image";
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1021-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 4MB for Linux Kernel Image */
reg = <0x00200000 0x00400000>;
label = "NAND Linux Kernel Image";
};
partition@600000 {
/* 4MB for Compressed Root file System Image */
reg = <0x00600000 0x00400000>;
label = "NAND Compressed RFS Image";
};
partition@a00000 {
/* 7MB for JFFS2 based Root file System */
reg = <0x00a00000 0x00700000>;
label = "NAND JFFS2 Root File System";
};
partition@1100000 {
/* 15MB for User Writable Area */
reg = <0x01100000 0x00f00000>;
label = "NAND Writable User area";
};
};
L2switch@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "vitesse-7385";
reg = <0x2 0x0 0x20000>;
};
};
&soc {
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "SPI Flash U-Boot Image";
read-only;
};
partition@dtb {
/* 512KB for DTB Image */
reg = <0x00080000 0x00080000>;
label = "SPI Flash DTB Image";
};
partition@kernel {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "SPI Flash Linux Kernel Image";
};
partition@fs {
/* 4MB for Compressed RFS Image */
reg = <0x00500000 0x00400000>;
label = "SPI Flash Compressed RFSImage";
};
partition@jffs-fs {
/* 7MB for JFFS2 based RFS */
reg = <0x00900000 0x00700000>;
label = "SPI Flash JFFS2 RFS";
};
};
};
usb@22000 {
phy_type = "ulpi";
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
tbi-handle = <&tbi2>;
phy-connection-type = "rgmii-id";
};
};
arch/powerpc/boot/dts/p1021rdb_36b.dts 0 → 100644
View file @ 5375871d
/*
* P1021 RDB Device Tree Source (36-bit address map)
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1021si-pre.dtsi"
/ {
model = "fsl,P1021RDB";
compatible = "fsl,P1021RDB-PC";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0xf 0xef000000 0x01000000
0x1 0x0 0xf 0xff800000 0x00040000
0x2 0x0 0xf 0xffb00000 0x00020000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
reg = <0xf 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
qe: qe@fffe80000 {
ranges = <0x0 0xf 0xffe80000 0x40000>;
reg = <0xf 0xffe80000 0 0x480>;
brg-frequency = <0>;
bus-frequency = <0>;
};
};
/include/ "p1021rdb.dtsi"
/include/ "fsl/p1021si-post.dtsi"
arch/powerpc/boot/dts/p1022ds.dts deleted 100644 → 0
View file @ b57cb723
/*
* P1022 DS 36Bit Physical Address Map Device Tree Source
*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "fsl/p1022si-pre.dtsi"
/ {
model = "fsl,P1022DS";
compatible = "fsl,P1022DS";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x1 0x0 0xf 0xe0000000 0x08000000
0x2 0x0 0xf 0xff800000 0x00040000
0x3 0x0 0xf 0xffdf0000 0x00008000>;
/*
* This node is used to access the pixis via "indirect" mode,
* which is done by writing the pixis register index to chip
* select 0 and the value to/from chip select 1. Indirect
* mode is the only way to access the pixis when DIU video
* is enabled. Note that this assumes that the first column
* of the 'ranges' property above is the chip select number.
*/
board-control@0,0 {
compatible = "fsl,p1022ds-indirect-pixis";
reg = <0x0 0x0 1 /* CS0 */
0x1 0x0 1>; /* CS1 */
};
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x03000000>;
label = "ramdisk-nor";
read-only;
};
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
partition@4000000 {
reg = <0x04000000 0x00400000>;
label = "kernel-nor";
read-only;
};
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "jffs2-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00080000>;
label = "dtb-nor";
read-only;
};
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "jffs2-nand";
};
partition@12000000 {
reg = <0x12000000 0x10000000>;
label = "ramdisk-nand";
read-only;
};
partition@22000000 {
reg = <0x22000000 0x04000000>;
label = "kernel-nand";
};
partition@26000000 {
reg = <0x26000000 0x01000000>;
label = "dtb-nand";
read-only;
};
partition@27000000 {
reg = <0x27000000 0x19000000>;
label = "reserved-nand";
};
};
board-control@3,0 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
interrupt-parent = <&mpic>;
/*
* IRQ8 is generated if the "EVENT" switch is pressed
* and PX_CTL[EVESEL] is set to 00.
*/
interrupts = <8 8 0 0>;
};
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
i2c@3100 {
wm8776:codec@1a {
compatible = "wlf,wm8776";
reg = <0x1a>;
/*
* clock-frequency will be set by U-Boot if
* the clock is enabled.
*/
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@0 {
label = "u-boot-spi";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "kernel-spi";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@600000 {
label = "dtb-spi";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@700000 {
label = "file system-spi";
reg = <0x00700000 0x00900000>;
};
};
};
ssi@15000 {
fsl,mode = "i2s-slave";
codec-handle = <&wm8776>;
fsl,ssi-asynchronous;
};
usb@22000 {
phy_type = "ulpi";
};
usb@23000 {
status = "disabled";
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x1>;
};
phy1: ethernet-phy@1 {
interrupts = <9 1 0 0>;
reg = <0x2>;
};
tbi-phy@2 {
device_type = "tbi-phy";
reg = <0x2>;
};
};
ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
ethernet@b1000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@fffe0b000 {
reg = <0xf 0xffe0b000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/p1022si-post.dtsi"
arch/powerpc/boot/dts/p1022ds.dtsi 0 → 100644
View file @ 5375871d
/*
* P1022 DS Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&board_lbc {
/*
* This node is used to access the pixis via "indirect" mode,
* which is done by writing the pixis register index to chip
* select 0 and the value to/from chip select 1. Indirect
* mode is the only way to access the pixis when DIU video
* is enabled. Note that this assumes that the first column
* of the 'ranges' property above is the chip select number.
*/
board-control@0,0 {
compatible = "fsl,p1022ds-indirect-pixis";
reg = <0x0 0x0 1 /* CS0 */
0x1 0x0 1>; /* CS1 */
interrupt-parent = <&mpic>;
interrupts = <8 0 0 0>;
};
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
reg = <0x0 0x03000000>;
label = "ramdisk-nor";
read-only;
};
partition@3000000 {
reg = <0x03000000 0x00e00000>;
label = "diagnostic-nor";
read-only;
};
partition@3e00000 {
reg = <0x03e00000 0x00200000>;
label = "dink-nor";
read-only;
};
partition@4000000 {
reg = <0x04000000 0x00400000>;
label = "kernel-nor";
read-only;
};
partition@4400000 {
reg = <0x04400000 0x03b00000>;
label = "jffs2-nor";
};
partition@7f00000 {
reg = <0x07f00000 0x00080000>;
label = "dtb-nor";
read-only;
};
partition@7f80000 {
reg = <0x07f80000 0x00080000>;
label = "u-boot-nor";
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
partition@0 {
reg = <0x0 0x02000000>;
label = "u-boot-nand";
read-only;
};
partition@2000000 {
reg = <0x02000000 0x10000000>;
label = "jffs2-nand";
};
partition@12000000 {
reg = <0x12000000 0x10000000>;
label = "ramdisk-nand";
read-only;
};
partition@22000000 {
reg = <0x22000000 0x04000000>;
label = "kernel-nand";
};
partition@26000000 {
reg = <0x26000000 0x01000000>;
label = "dtb-nand";
read-only;
};
partition@27000000 {
reg = <0x27000000 0x19000000>;
label = "reserved-nand";
};
};
board-control@3,0 {
compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
interrupt-parent = <&mpic>;
/*
* IRQ8 is generated if the "EVENT" switch is pressed
* and PX_CTL[EVESEL] is set to 00.
*/
interrupts = <8 0 0 0>;
};
};
&board_soc {
i2c@3100 {
wm8776:codec@1a {
compatible = "wlf,wm8776";
reg = <0x1a>;
/*
* clock-frequency will be set by U-Boot if
* the clock is enabled.
*/
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@0 {
label = "u-boot-spi";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "kernel-spi";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@600000 {
label = "dtb-spi";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@700000 {
label = "file system-spi";
reg = <0x00700000 0x00900000>;
};
};
};
ssi@15000 {
fsl,mode = "i2s-slave";
codec-handle = <&wm8776>;
fsl,ssi-asynchronous;
};
usb@22000 {
phy_type = "ulpi";
};
usb@23000 {
status = "disabled";
};
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x1>;
};
phy1: ethernet-phy@1 {
interrupts = <9 1 0 0>;
reg = <0x2>;
};
tbi-phy@2 {
device_type = "tbi-phy";
reg = <0x2>;
};
};
ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
ethernet@b1000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
arch/powerpc/boot/dts/p1022ds_32b.dts 0 → 100644
View file @ 5375871d
/*
* P1022 DS 32-bit Physical Address Map Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1022si-pre.dtsi"
/ {
model = "fsl,P1022DS";
compatible = "fsl,P1022DS";
memory {
device_type = "memory";
};
board_lbc: lbc: localbus@ffe05000 {
ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
0x1 0x0 0x0 0xe0000000 0x08000000
0x2 0x0 0x0 0xff800000 0x00040000
0x3 0x0 0x0 0xffdf0000 0x00008000>;
reg = <0x0 0xffe05000 0 0x1000>;
};
board_soc: soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0x0 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
reg = <0 0xffe0a000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@ffe0b000 {
ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
reg = <0 0xffe0b000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/p1022si-post.dtsi"
/include/ "p1022ds.dtsi"
arch/powerpc/boot/dts/p1022ds_36b.dts 0 → 100644
View file @ 5375871d
/*
* P1022 DS 36-bit Physical Address Map Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1022si-pre.dtsi"
/ {
model = "fsl,P1022DS";
compatible = "fsl,P1022DS";
memory {
device_type = "memory";
};
board_lbc: lbc: localbus@fffe05000 {
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x1 0x0 0xf 0xe0000000 0x08000000
0x2 0x0 0xf 0xff800000 0x00040000
0x3 0x0 0xf 0xffdf0000 0x00008000>;
reg = <0xf 0xffe05000 0 0x1000>;
};
board_soc: soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
reg = <0xf 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
reg = <0xf 0xffe0a000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@fffe0b000 {
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
reg = <0xf 0xffe0b000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "fsl/p1022si-post.dtsi"
/include/ "p1022ds.dtsi"
arch/powerpc/boot/dts/p1025rdb.dtsi 0 → 100644
View file @ 5375871d
/*
* P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
&lbc {
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x1000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* This location must not be altered */
/* 256KB for Vitesse 7385 Switch firmware */
reg = <0x0 0x00040000>;
label = "NOR Vitesse-7385 Firmware";
read-only;
};
partition@40000 {
/* 256KB for DTB Image */
reg = <0x00040000 0x00040000>;
label = "NOR DTB Image";
};
partition@80000 {
/* 3.5 MB for Linux Kernel Image */
reg = <0x00080000 0x00380000>;
label = "NOR Linux Kernel Image";
};
partition@400000 {
/* 11MB for JFFS2 based Root file System */
reg = <0x00400000 0x00b00000>;
label = "NOR JFFS2 Root File System";
};
partition@f00000 {
/* This location must not be altered */
/* 512KB for u-boot Bootloader Image */
/* 512KB for u-boot Environment Variables */
reg = <0x00f00000 0x00100000>;
label = "NOR U-Boot Image";
read-only;
};
};
nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1025-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND DTB Image";
};
partition@200000 {
/* 4MB for Linux Kernel Image */
reg = <0x00200000 0x00400000>;
label = "NAND Linux Kernel Image";
};
partition@600000 {
/* 4MB for Compressed Root file System Image */
reg = <0x00600000 0x00400000>;
label = "NAND Compressed RFS Image";
};
partition@a00000 {
/* 7MB for JFFS2 based Root file System */
reg = <0x00a00000 0x00700000>;
label = "NAND JFFS2 Root File System";
};
partition@1100000 {
/* 15MB for JFFS2 based Root file System */
reg = <0x01100000 0x00f00000>;
label = "NAND Writable User area";
};
};
};
&soc {
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
/* 512KB for u-boot Bootloader Image */
reg = <0x0 0x00080000>;
label = "u-boot";
read-only;
};
partition@dtb {
/* 512KB for DTB Image */
reg = <0x00080000 0x00080000>;
label = "dtb";
};
partition@kernel {
/* 4MB for Linux Kernel Image */
reg = <0x00100000 0x00400000>;
label = "kernel";
};
partition@fs {
/* 4MB for Compressed RFS Image */
reg = <0x00500000 0x00400000>;
label = "file system";
};
partition@jffs-fs {
/* 7MB for JFFS2 based RFS */
reg = <0x00900000 0x00700000>;
label = "file system jffs2";
};
};
};
usb@22000 {
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
phy_type = "ulpi";
};
*/
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
par_io@e0100 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe0100 0x60>;
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
};
};
};
arch/powerpc/boot/dts/p1025rdb_32b.dts 0 → 100644
View file @ 5375871d
/*
* P1025 RDB Device Tree Source (32-bit address map)
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1021si-pre.dtsi"
/ {
model = "fsl,P1025RDB";
compatible = "fsl,P1025RDB";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xff800000 0x00040000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe09000 {
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
qe: qe@ffe80000 {
ranges = <0x0 0x0 0xffe80000 0x40000>;
reg = <0 0xffe80000 0 0x480>;
brg-frequency = <0>;
bus-frequency = <0>;
status = "disabled"; /* no firmware loaded */
enet3: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
rx-clock-name = "clk12";
tx-clock-name = "clk9";
pio-handle = <&pio1>;
phy-handle = <&qe_phy0>;
phy-connection-type = "mii";
};
mdio@2120 {
qe_phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <4 1 0 0>;
reg = <0x6>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@03 {
interrupt-parent = <&mpic>;
interrupts = <5 1 0 0>;
reg = <0x3>;
device_type = "ethernet-phy";
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet4: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
rx-clock-name = "none";
tx-clock-name = "clk13";
pio-handle = <&pio2>;
phy-handle = <&qe_phy1>;
phy-connection-type = "rmii";
};
};
};
/include/ "p1025rdb.dtsi"
/include/ "fsl/p1021si-post.dtsi"
arch/powerpc/boot/dts/p1025rdb_36b.dts 0 → 100644
View file @ 5375871d
/*
* P1025 RDB Device Tree Source (36-bit address map)
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p1021si-pre.dtsi"
/ {
model = "fsl,P1025RDB";
compatible = "fsl,P1025RDB";
memory {
device_type = "memory";
};
lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
/* NOR, NAND Flashes */
ranges = <0x0 0x0 0xf 0xef000000 0x01000000
0x1 0x0 0xf 0xff800000 0x00040000>;
};
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p1025rdb.dtsi"
/include/ "fsl/p1021si-post.dtsi"
arch/powerpc/boot/dts/p2020rdb-pc.dtsi 0 → 100644
View file @ 5375871d
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arch/powerpc/boot/dts/p2020rdb-pc_32b.dts 0 → 100644
View file @ 5375871d
/*
* P2020 RDB-PC 32Bit Physical Address Map Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/include/ "fsl/p2020si-pre.dtsi"
/ {
model = "fsl,P2020RDB";
compatible = "fsl,P2020RDB-PC";
memory {
device_type = "memory";
};
lbc: localbus@ffe05000 {
reg = <0 0xffe05000 0 0x1000>;
/* NOR and NAND Flashes */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000
0x3 0x0 0x0 0xffa00000 0x00020000>;
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci0: pcie@ffe08000 {
reg = <0 0xffe08000 0 0x1000>;
status = "disabled";
};
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci2: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
0x2000000 0x0 0xe0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
};
/include/ "p2020rdb-pc.dtsi"
/include/ "fsl/p2020si-post.dtsi"
arch/powerpc/boot/dts/p2020rdb-pc_36b.dts 0 → 100644
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arch/powerpc/boot/dts/p2020rdb.dts
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......@@ -34,7 +34,7 @@ lbc: localbus@ffe05000 {
/* NOR and NAND Flashes */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
0x1 0x0 0x0 0xffa00000 0x00040000
0x1 0x0 0x0 0xff800000 0x00040000
0x2 0x0 0x0 0xffb00000 0x00020000>;
nor@0,0 {
......@@ -157,7 +157,7 @@ flash@0 {
#size-cells = <1>;
compatible = "spansion,s25sl12801";
reg = <0>;
spi-max-frequency = <50000000>;
spi-max-frequency = <40000000>;
partition@0 {
/* 512KB for u-boot Bootloader Image */
......
arch/powerpc/boot/wrapper
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arch/powerpc/configs/86xx/gef_ppc9a_defconfig
View file @ 5375871d
......@@ -131,6 +131,7 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GE_FPGA=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM92=y
CONFIG_WATCHDOG=y
......
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CONFIG_PPC_85xx=y
CONFIG_PHYS_64BIT=y
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
......
arch/powerpc/configs/mpc85xx_smp_defconfig
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