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Commit 571d54ed authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:

 - Convert various DT (non-binding) doc files to ReST

 - Various improvements to device link code

 - Fix __of_attach_node_sysfs refcounting bug

 - Add support for 'memory-region-names' with reserved-memory binding

 - Vendor prefixes for Protonic Holland, BeagleBoard.org, Alps, Check
   Point, Würth Elektronik, U-Boot, Vaisala, Baikal Electronics,
   Shanghai Awinic Technology Co., MikroTik, Silex Insight

 - A bunch more binding conversions to DT schema. Only 3K to go.

 - Add a minimum version check for schema tools

 - Treewide dropping of 'allOf' usage with schema references. Not needed
   in new json-schema spec.

 - Some formatting clean-ups of schemas

* tag 'devicetree-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (194 commits)
  dt-bindings: clock: Add documentation for X1830 bindings.
  dt-bindings: mailbox: Convert imx mu to json-schema
  dt-bindings: power: Convert imx gpcv2 to json-schema
  dt-bindings: power: Convert imx gpc to json-schema
  dt-bindings: Merge gpio-usb-b-connector with usb-connector
  dt-bindings: timer: renesas: cmt: Convert to json-schema
  dt-bindings: clock: Convert i.MX8QXP LPCG to json-schema
  dt-bindings: timer: Convert i.MX GPT to json-schema
  dt-bindings: thermal: rcar-thermal: Add device tree support for r8a7742
  dt-bindings: serial: Add binding for UART pin swap
  dt-bindings: geni-se: Add interconnect binding for GENI QUP
  dt-bindings: geni-se: Convert QUP geni-se bindings to YAML
  dt-bindings: vendor-prefixes: Add Silex Insight vendor prefix
  dt-bindings: input: touchscreen: edt-ft5x06: change reg property
  dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver
  dt-bindings: timer: renesas: mtu2: Convert to json-schema
  of/fdt: Remove redundant kbasename function call
  dt-bindings: clock: Convert i.MX1 clock to json-schema
  dt-bindings: clock: Convert i.MX21 clock to json-schema
  dt-bindings: clock: Convert i.MX25 clock to json-schema
  ...
parents 9d71d3cd 8211d1e8
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Documentation/arm/microchip.rst
View file @ 571d54ed
......@@ -192,7 +192,7 @@ Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards ar
considered as "Unstable". To be completely clear, any at91 binding can change at
any time. So, be sure to use a Device Tree Binary and a Kernel Image generated from
the same source tree.
Please refer to the Documentation/devicetree/bindings/ABI.txt file for a
Please refer to the Documentation/devicetree/bindings/ABI.rst file for a
definition of a "Stable" binding/ABI.
This statement will be removed by AT91 MAINTAINERS when appropriate.
......
Documentation/devicetree/bindings/ABI.txt → Documentation/devicetree/bindings/ABI.rst
View file @ 571d54ed
.. SPDX-License-Identifier: GPL-2.0
Devicetree (DT) ABI
===================
Devicetree (DT) ABI
===================
I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit
summary document:
......
Documentation/devicetree/bindings/Makefile
View file @ 571d54ed
......@@ -4,11 +4,19 @@ DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
DT_MK_SCHEMA_USERONLY_FLAG := $(if $(DT_SCHEMA_FILES), -u)
DT_SCHEMA_MIN_VERSION = 2020.5
PHONY += check_dtschema_version
check_dtschema_version:
@{ echo $(DT_SCHEMA_MIN_VERSION); \
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml FORCE
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
$(call if_changed,chk_binding)
# Use full schemas when checking %.example.dts
......@@ -37,11 +45,11 @@ override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address
$(obj)/processed-schema-examples.yaml: $(DT_DOCS) FORCE
$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE
$(call if_changed,mk_schema)
$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := $(DT_MK_SCHEMA_USERONLY_FLAG)
$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) FORCE
$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
$(call if_changed,mk_schema)
extra-y += processed-schema.yaml
Documentation/devicetree/bindings/arm/altera.yaml
View file @ 571d54ed
......@@ -13,8 +13,8 @@ properties:
compatible:
items:
- enum:
- altr,socfpga-cyclone5
- altr,socfpga-arria5
- altr,socfpga-arria10
- altr,socfpga-cyclone5
- altr,socfpga-arria5
- altr,socfpga-arria10
- const: altr,socfpga
...
Documentation/devicetree/bindings/arm/amlogic.yaml
View file @ 571d54ed
......@@ -17,7 +17,7 @@ description: |+
any time. Be sure to use a device tree binary and a kernel image
generated from the same source tree.
Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.
properties:
......
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
View file @ 571d54ed
......@@ -25,7 +25,7 @@ select:
properties:
compatible:
items:
items:
- const: amlogic,meson-gx-ao-secure
- const: syscon
......
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
View file @ 571d54ed
......@@ -131,26 +131,23 @@ properties:
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
allOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- minimum: 0
maximum: 15
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 15
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
allOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- minimum: 0
maximum: 3
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 3
arm,vexpress,dcc:
description: When describing tiles consisting of more than one DCC, its
number can be specified with this attribute.
allOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- minimum: 0
maximum: 3
$ref: '/schemas/types.yaml#/definitions/uint32'
minimum: 0
maximum: 3
patternProperties:
"^bus@[0-9a-f]+$":
......@@ -162,8 +159,7 @@ patternProperties:
"simple-bus". If the compatible is placed in the "motherboard" node,
it is stricter and always has two compatibles.
type: object
allOf:
- $ref: '/schemas/simple-bus.yaml'
$ref: '/schemas/simple-bus.yaml'
properties:
compatible:
......@@ -195,11 +191,11 @@ patternProperties:
- const: simple-bus
arm,v2m-memory-map:
description: This describes the memory map type.
allOf:
- $ref: '/schemas/types.yaml#/definitions/string'
- enum:
- rs1
- rs2
$ref: '/schemas/types.yaml#/definitions/string'
enum:
- rs1
- rs2
required:
- compatible
required:
......
Documentation/devicetree/bindings/arm/bitmain.yaml
View file @ 571d54ed
......@@ -13,6 +13,6 @@ properties:
compatible:
items:
- enum:
- bitmain,sophon-edge
- bitmain,sophon-edge
- const: bitmain,bm1880
...
Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Highbank system registers
description: |
The Calxeda Highbank system has a block of MMIO registers controlling
several generic system aspects. Those can be used to control some power
management, they also contain some gate and PLL clocks.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: calxeda,hb-sregs
reg:
maxItems: 1
clocks:
type: object
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sregs@fff3c000 {
compatible = "calxeda,hb-sregs";
reg = <0xfff3c000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333000>;
};
};
};
Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted 100644 → 0
View file @ 9d71d3cd
Calxeda Highbank L2 cache ECC
Properties:
- compatible : Should be "calxeda,hb-sregs-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt.
Example:
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
interrupts = <0 71 4 0 72 4>;
};
Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Highbank L2 cache ECC
description: |
Binding for the Calxeda Highbank L2 cache controller ECC device.
This does not cover the actual L2 cache controller control registers,
but just the error reporting functionality.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
reg:
maxItems: 1
interrupts:
items:
- description: single bit error interrupt
- description: double bit error interrupt
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
interrupts = <0 71 4>, <0 72 4>;
};
Documentation/devicetree/bindings/arm/coresight-cti.yaml
View file @ 571d54ed
......@@ -140,16 +140,14 @@ patternProperties:
maxItems: 1
arm,trig-in-sigs:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger in signal numbers in use by a trig-conns node.
arm,trig-in-types:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
......@@ -159,16 +157,14 @@ patternProperties:
completely, then the types will default to GEN_IO.
arm,trig-out-sigs:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
List of CTI trigger out signal numbers in use by a trig-conns node.
arm,trig-out-types:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
......@@ -178,8 +174,7 @@ patternProperties:
or omitted completely, then the types will default to GEN_IO.
arm,trig-filters:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 32
description:
......@@ -187,8 +182,7 @@ patternProperties:
active, unless filtering is disabled on the driver.
arm,trig-conn-name:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
$ref: /schemas/types.yaml#/definitions/string
description:
Defines a connection name that will be displayed, if the cpu or
arm,cs-dev-assoc properties are not being used in this connection.
......@@ -301,7 +295,7 @@ examples:
- |
cti@20110000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0 0x20110000 0 0x1000>;
reg = <0x20110000 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
......
Documentation/devicetree/bindings/arm/cpus.yaml
View file @ 571d54ed
......@@ -172,49 +172,48 @@ properties:
- qcom,scorpion
enable-method:
allOf:
- $ref: '/schemas/types.yaml#/definitions/string'
- oneOf:
# On ARM v8 64-bit this property is required
- enum:
- psci
- spin-table
# On ARM 32-bit systems this property is optional
- enum:
- actions,s500-smp
- allwinner,sun6i-a31
- allwinner,sun8i-a23
- allwinner,sun9i-a80-smp
- allwinner,sun8i-a83t-smp
- amlogic,meson8-smp
- amlogic,meson8b-smp
- arm,realview-smp
- aspeed,ast2600-smp
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm2836-smp
- brcm,bcm63138
- brcm,bcm-nsp-smp
- brcm,brahma-b15
- marvell,armada-375-smp
- marvell,armada-380-smp
- marvell,armada-390-smp
- marvell,armada-xp-smp
- marvell,98dx3236-smp
- marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
- qcom,gcc-msm8660
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- renesas,apmu
- renesas,r9a06g032-smp
- rockchip,rk3036-smp
- rockchip,rk3066-smp
- socionext,milbeaut-m10v-smp
- ste,dbx500-smp
- ti,am3352
- ti,am4372
$ref: '/schemas/types.yaml#/definitions/string'
oneOf:
# On ARM v8 64-bit this property is required
- enum:
- psci
- spin-table
# On ARM 32-bit systems this property is optional
- enum:
- actions,s500-smp
- allwinner,sun6i-a31
- allwinner,sun8i-a23
- allwinner,sun9i-a80-smp
- allwinner,sun8i-a83t-smp
- amlogic,meson8-smp
- amlogic,meson8b-smp
- arm,realview-smp
- aspeed,ast2600-smp
- brcm,bcm11351-cpu-method
- brcm,bcm23550
- brcm,bcm2836-smp
- brcm,bcm63138
- brcm,bcm-nsp-smp
- brcm,brahma-b15
- marvell,armada-375-smp
- marvell,armada-380-smp
- marvell,armada-390-smp
- marvell,armada-xp-smp
- marvell,98dx3236-smp
- marvell,mmp3-smp
- mediatek,mt6589-smp
- mediatek,mt81xx-tz-smp
- qcom,gcc-msm8660
- qcom,kpss-acc-v1
- qcom,kpss-acc-v2
- renesas,apmu
- renesas,r9a06g032-smp
- rockchip,rk3036-smp
- rockchip,rk3066-smp
- socionext,milbeaut-m10v-smp
- ste,dbx500-smp
- ti,am3352
- ti,am4372
cpu-release-addr:
$ref: '/schemas/types.yaml#/definitions/uint64'
......
Documentation/devicetree/bindings/arm/l2c2x0.yaml
View file @ 571d54ed
......@@ -70,43 +70,39 @@ properties:
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
read, write and setup latencies. Minimum valid values are 1. Controllers
without setup latency control should use a value of 0.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 2
maxItems: 3
items:
minimum: 0
maximum: 8
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 3
items:
minimum: 0
maximum: 8
arm,tag-latency:
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
read, write and setup latencies. Controllers without setup latency control
should use 0. Controllers without separate read and write Tag RAM latency
values should only use the first cell.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 3
items:
minimum: 0
maximum: 8
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 3
items:
minimum: 0
maximum: 8
arm,dirty-latency:
description: Cycles of latency for Dirty RAMs. This is a single cell.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
maximum: 8
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 8
arm,filter-ranges:
description: <start length> Starting address and length of window to
filter. Addresses in the filter window are directed to the M1 port. Other
addresses will go to the M0 port.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- items:
minItems: 2
maxItems: 2
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
minItems: 2
maxItems: 2
arm,io-coherent:
description: indicates that the system is operating in an hardware
......@@ -131,36 +127,31 @@ properties:
arm,double-linefill:
description: Override double linefill enable setting. Enable if
non-zero, disable if zero.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,double-linefill-incr:
description: Override double linefill on INCR read. Enable
if non-zero, disable if zero.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,double-linefill-wrap:
description: Override double linefill on WRAP read. Enable
if non-zero, disable if zero.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,prefetch-drop:
description: Override prefetch drop enable setting. Enable if non-zero,
disable if zero.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,prefetch-offset:
description: Override prefetch offset value.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
arm,shared-override:
description: The default behavior of the L220 or PL310 cache
......@@ -193,35 +184,31 @@ properties:
description: |
Data prefetch. Value: <0> (forcibly disable), <1>
(forcibly enable), property absent (retain settings set by firmware)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
prefetch-instr:
description: |
Instruction prefetch. Value: <0> (forcibly disable),
<1> (forcibly enable), property absent (retain settings set by
firmware)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,dynamic-clock-gating:
description: |
L2 dynamic clock gating. Value: <0> (forcibly
disable), <1> (forcibly enable), property absent (OS specific behavior,
preferably retain firmware settings)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,standby-mode:
description: L2 standby mode enable. Value <0> (forcibly disable),
<1> (forcibly enable), property absent (OS specific behavior,
preferably retain firmware settings)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
arm,early-bresp-disable:
description: Disable the CA9 optimization Early BRESP (PL310)
......
Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
View file @ 571d54ed
......@@ -17,9 +17,8 @@ properties:
- nxp,lpc3230
- nxp,lpc3240
- items:
- enum:
- ea,ea3250
- phytec,phy3250
- const: nxp,lpc3250
- enum:
- ea,ea3250
- phytec,phy3250
- const: nxp,lpc3250
...
Documentation/devicetree/bindings/arm/psci.yaml
View file @ 571d54ed
......@@ -69,13 +69,11 @@ properties:
method:
description: The method of calling the PSCI firmware.
allOf:
- $ref: /schemas/types.yaml#/definitions/string-array
- enum:
# SMC #0, with the register assignments specified in this binding.
- smc
# HVC #0, with the register assignments specified in this binding.
- hvc
$ref: /schemas/types.yaml#/definitions/string-array
enum:
- smc
# HVC #0, with the register assignments specified in this binding.
- hvc
cpu_suspend:
$ref: /schemas/types.yaml#/definitions/uint32
......@@ -107,8 +105,8 @@ properties:
patternProperties:
"^power-domain-":
allOf:
- $ref: "../power/power-domain.yaml#"
$ref: "../power/power-domain.yaml#"
type: object
description: |
ARM systems can have multiple cores, sometimes in an hierarchical
......
Documentation/devicetree/bindings/arm/renesas,prr.yaml
View file @ 571d54ed
......@@ -33,5 +33,5 @@ examples:
- |
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
reg = <0xff000044 4>;
};
Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
View file @ 571d54ed
......@@ -22,9 +22,8 @@ properties:
Adaptive Supply Voltage bin selection. This can be used
to determine the ASV bin of an SoC if respective information
is missing in the CHIPID registers or in the OTP memory.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
required:
- compatible
......
Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
View file @ 571d54ed
......@@ -17,46 +17,46 @@ properties:
- description: LD4 SoC boards
items:
- enum:
- socionext,uniphier-ld4-ref
- socionext,uniphier-ld4-ref
- const: socionext,uniphier-ld4
- description: Pro4 SoC boards
items:
- enum:
- socionext,uniphier-pro4-ace
- socionext,uniphier-pro4-ref
- socionext,uniphier-pro4-sanji
- socionext,uniphier-pro4-ace
- socionext,uniphier-pro4-ref
- socionext,uniphier-pro4-sanji
- const: socionext,uniphier-pro4
- description: sLD8 SoC boards
items:
- enum:
- socionext,uniphier-sld8-ref
- socionext,uniphier-sld8-ref
- const: socionext,uniphier-sld8
- description: PXs2 SoC boards
items:
- enum:
- socionext,uniphier-pxs2-gentil
- socionext,uniphier-pxs2-vodka
- socionext,uniphier-pxs2-gentil
- socionext,uniphier-pxs2-vodka
- const: socionext,uniphier-pxs2
- description: LD6b SoC boards
items:
- enum:
- socionext,uniphier-ld6b-ref
- socionext,uniphier-ld6b-ref
- const: socionext,uniphier-ld6b
- description: LD11 SoC boards
items:
- enum:
- socionext,uniphier-ld11-global
- socionext,uniphier-ld11-ref
- socionext,uniphier-ld11-global
- socionext,uniphier-ld11-ref
- const: socionext,uniphier-ld11
- description: LD20 SoC boards
items:
- enum:
- socionext,uniphier-ld20-akebi96
- socionext,uniphier-ld20-global
- socionext,uniphier-ld20-ref
- socionext,uniphier-ld20-akebi96
- socionext,uniphier-ld20-global
- socionext,uniphier-ld20-ref
- const: socionext,uniphier-ld20
- description: PXs3 SoC boards
items:
- enum:
- socionext,uniphier-pxs3-ref
- socionext,uniphier-pxs3-ref
- const: socionext,uniphier-pxs3
Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml
View file @ 571d54ed
......@@ -20,7 +20,7 @@ description: |
[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
allOf:
- $ref: /schemas/simple-bus.yaml#
- $ref: /schemas/simple-bus.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
View file @ 571d54ed
......@@ -14,9 +14,9 @@ properties:
compatible:
oneOf:
- items:
- enum:
- st,stm32mp157-syscfg
- const: syscon
- enum:
- st,stm32mp157-syscfg
- const: syscon
reg:
maxItems: 1
......
Documentation/devicetree/bindings/arm/syna.txt
View file @ 571d54ed
......@@ -13,7 +13,7 @@ considered "unstable". Any Marvell Berlin device tree binding may change at any
time. Be sure to use a device tree binary and a kernel image generated from the
same source tree.
Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.
---------------------------------------------------------------
......
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View file @ 571d54ed
......@@ -323,7 +323,7 @@ examples:
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
......
Documentation/devicetree/bindings/ata/faraday,ftide010.yaml
View file @ 571d54ed
......@@ -26,8 +26,8 @@ properties:
oneOf:
- const: faraday,ftide010
- items:
- const: cortina,gemini-pata
- const: faraday,ftide010
- const: cortina,gemini-pata
- const: faraday,ftide010
reg:
maxItems: 1
......
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
View file @ 571d54ed
......@@ -17,6 +17,7 @@ properties:
- renesas,sata-r8a7779 # R-Car H1
- items:
- enum:
- renesas,sata-r8a7742 # RZ/G1H
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
- renesas,sata-r8a7790 # R-Car H2 other than ES1
- renesas,sata-r8a7791 # R-Car M2-W
......
Documentation/devicetree/bindings/ata/sata_highbank.txt deleted 100644 → 0
View file @ 9d71d3cd
* Calxeda AHCI SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
The Calxeda SATA controller mostly conforms to the AHCI interface
with some special extensions to add functionality.
Each SATA controller should have its own node.
Required properties:
- compatible : compatible list, contains "calxeda,hb-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
Optional properties:
- dma-coherent : Present if dma operations are coherent
- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
SATA port to a combophy and a lane within that
combophy
- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
which indicates that the driver supports SGPIO
indicator lights using the indicated GPIOs
- calxeda,led-order : a u32 array that map port numbers to offsets within the
SGPIO bitstream.
- calxeda,tx-atten : a u32 array that contains TX attenuation override
codes, one per port. The upper 3 bytes are always
0 and thus ignored.
- calxeda,pre-clocks : a u32 that indicates the number of additional clock
cycles to transmit before sending an SGPIO pattern
- calxeda,post-clocks: a u32 that indicates the number of additional clock
cycles to transmit after sending an SGPIO pattern
Example:
sata@ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
dma-coherent;
calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
&combophy0 2 &combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
calxeda,pre-clocks = <10>;
calxeda,post-clocks = <0>;
};
Documentation/devicetree/bindings/ata/sata_highbank.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda AHCI SATA Controller
description: |
The Calxeda SATA controller mostly conforms to the AHCI interface
with some special extensions to add functionality, to map GPIOs for
activity LEDs and for mapping the ComboPHYs.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: calxeda,hb-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
dma-coherent: true
calxeda,pre-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit before
sending an SGPIO pattern.
calxeda,post-clocks:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Indicates the number of additional clock cycles to transmit after
sending an SGPIO pattern.
calxeda,led-order:
description: Maps port numbers to offsets within the SGPIO bitstream.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 8
calxeda,port-phys:
description: |
phandle-combophy and lane assignment, which maps each SATA port to a
combophy and a lane within that combophy
allOf:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- minItems: 1
maxItems: 8
calxeda,tx-atten:
description: |
Contains TX attenuation override codes, one per port.
The upper 24 bits of each entry are always 0 and thus ignored.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 8
calxeda,sgpio-gpio:
description: |
phandle-gpio bank, bit offset, and default on or off, which indicates
that the driver supports SGPIO indicator lights using the indicated
GPIOs.
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sata@ffe08000 {
compatible = "calxeda,hb-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
dma-coherent;
calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
<&combophy0 2>, <&combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
calxeda,pre-clocks = <10>;
calxeda,post-clocks = <0>;
};
...
Documentation/devicetree/bindings/auxdisplay/hit,hd44780.txt deleted 100644 → 0
View file @ 9d71d3cd
DT bindings for the Hitachi HD44780 Character LCD Controller
The Hitachi HD44780 Character LCD Controller is commonly used on character LCDs
that can display one or more lines of text. It exposes an M6800 bus interface,
which can be used in either 4-bit or 8-bit mode.
Required properties:
- compatible: Must contain "hit,hd44780",
- data-gpios: Must contain an array of either 4 or 8 GPIO specifiers,
referring to the GPIO pins connected to the data signal lines DB0-DB7
(8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface,
- enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin
connected to the "E" (Enable) signal line of the LCD Controller's bus
interface,
- rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin
connected to the "RS" (Register Select) signal line of the LCD Controller's
bus interface,
- display-height-chars: Height of the display, in character cells,
- display-width-chars: Width of the display, in character cells.
Optional properties:
- rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin
connected to the "RW" (Read/Write) signal line of the LCD Controller's bus
interface,
- backlight-gpios: Must contain a GPIO specifier, referring to the GPIO pin
used for enabling the LCD's backlight,
- internal-buffer-width: Internal buffer width (default is 40 for displays
with 1 or 2 lines, and display-width-chars for displays with more than 2
lines).
Example:
auxdisplay {
compatible = "hit,hd44780";
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
<&hc595 1 GPIO_ACTIVE_HIGH>,
<&hc595 2 GPIO_ACTIVE_HIGH>,
<&hc595 3 GPIO_ACTIVE_HIGH>;
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
display-height-chars = <2>;
display-width-chars = <16>;
};
Documentation/devicetree/bindings/auxdisplay/hit,hd44780.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/hit,hd44780.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hitachi HD44780 Character LCD Controller
maintainers:
- Geert Uytterhoeven <geert@linux-m68k.org>
description:
The Hitachi HD44780 Character LCD Controller is commonly used on character
LCDs that can display one or more lines of text. It exposes an M6800 bus
interface, which can be used in either 4-bit or 8-bit mode.
properties:
compatible:
const: hit,hd44780
data-gpios:
description:
GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
oneOf:
- maxItems: 4
- maxItems: 8
enable-gpios:
description:
GPIO pin connected to the "E" (Enable) signal line of the LCD
Controller's bus interface.
maxItems: 1
rs-gpios:
description:
GPIO pin connected to the "RS" (Register Select) signal line of the LCD
Controller's bus interface.
maxItems: 1
rw-gpios:
description:
GPIO pin connected to the "RW" (Read/Write) signal line of the LCD
Controller's bus interface.
maxItems: 1
backlight-gpios:
description: GPIO pin used for enabling the LCD's backlight.
maxItems: 1
display-height-chars:
description: Height of the display, in character cells,
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 4
display-width-chars:
description: Width of the display, in character cells.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 64
internal-buffer-width:
description:
Internal buffer width (default is 40 for displays with 1 or 2 lines, and
display-width-chars for displays with more than 2 lines).
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 64
required:
- compatible
- data-gpios
- enable-gpios
- rs-gpios
- display-height-chars
- display-width-chars
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
auxdisplay {
compatible = "hit,hd44780";
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
<&hc595 1 GPIO_ACTIVE_HIGH>,
<&hc595 2 GPIO_ACTIVE_HIGH>,
<&hc595 3 GPIO_ACTIVE_HIGH>;
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
display-height-chars = <2>;
display-width-chars = <16>;
};
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
View file @ 571d54ed
......@@ -31,12 +31,11 @@ properties:
maxItems: 1
allwinner,sram:
allOf:
- $ref: /schemas/types.yaml#definitions/phandle-array
- maxItems: 1
description:
The SRAM that needs to be claimed to access the display engine
bus.
$ref: /schemas/types.yaml#definitions/phandle-array
maxItems: 1
ranges: true
......
Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml
View file @ 571d54ed
......@@ -21,8 +21,8 @@ properties:
oneOf:
- const: allwinner,sun8i-a23-rsb
- items:
- const: allwinner,sun8i-a83t-rsb
- const: allwinner,sun8i-a23-rsb
- const: allwinner,sun8i-a83t-rsb
- const: allwinner,sun8i-a23-rsb
reg:
maxItems: 1
......
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-gates-clk.yaml
View file @ 571d54ed
......@@ -52,12 +52,12 @@ properties:
- const: allwinner,sun4i-a10-dram-gates-clk
- items:
- const: allwinner,sun5i-a13-dram-gates-clk
- const: allwinner,sun4i-a10-gates-clk
- const: allwinner,sun5i-a13-dram-gates-clk
- const: allwinner,sun4i-a10-gates-clk
- items:
- const: allwinner,sun8i-h3-apb0-gates-clk
- const: allwinner,sun4i-a10-gates-clk
- const: allwinner,sun8i-h3-apb0-gates-clk
- const: allwinner,sun4i-a10-gates-clk
reg:
maxItems: 1
......
Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
View file @ 571d54ed
......@@ -65,7 +65,7 @@ examples:
- |
uart0: serial@58018000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x58018000 0x0 0x2000>;
reg = <0x58018000 0x2000>;
clocks = <&clk 45>, <&clk 46>;
clock-names = "baudclk", "apb_pclk";
interrupts = <0 9 4>;
......
Documentation/devicetree/bindings/clock/calxeda.txt deleted 100644 → 0
View file @ 9d71d3cd
Device Tree Clock bindings for Calxeda highbank platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"calxeda,hb-pll-clock" - for a PLL clock
"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
A9 clock.
"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
- reg : shall be the control register offset from SYSREGs base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding; shall be set to 0.
Documentation/devicetree/bindings/clock/calxeda.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/calxeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Device Tree Clock bindings for Calxeda highbank platform
description: |
This binding covers the Calxeda SoC internal peripheral and bus clocks
as used by peripherals. The clocks live inside the "system register"
region of the SoC, so are typically presented as children of an
"hb-sregs" node.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
"#clock-cells":
const: 0
compatible:
enum:
- calxeda,hb-pll-clock
- calxeda,hb-a9periph-clock
- calxeda,hb-a9bus-clock
- calxeda,hb-emmc-clock
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- "#clock-cells"
- compatible
- clocks
- reg
additionalProperties: false
examples:
- |
sregs@3fffc000 {
compatible = "calxeda,hb-sregs";
reg = <0x3fffc000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333000>;
};
ddrpll: ddrpll@108 {
#clock-cells = <0>;
compatible = "calxeda,hb-pll-clock";
clocks = <&osc>;
reg = <0x108>;
};
a9pll: a9pll@100 {
#clock-cells = <0>;
compatible = "calxeda,hb-pll-clock";
clocks = <&osc>;
reg = <0x100>;
};
a9periphclk: a9periphclk@104 {
#clock-cells = <0>;
compatible = "calxeda,hb-a9periph-clock";
clocks = <&a9pll>;
reg = <0x104>;
};
};
};
...
Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt deleted 100644 → 0
View file @ 9d71d3cd
Cirrus Logic Lochnagar Audio Development Board
Lochnagar is an evaluation and development board for Cirrus Logic
Smart CODEC and Amp devices. It allows the connection of most Cirrus
Logic devices on mini-cards, as well as allowing connection of
various application processor systems to provide a full evaluation
platform. Audio system topology, clocking and power can all be
controlled through the Lochnagar, allowing the device under test
to be used in a variety of possible use cases.
This binding document describes the binding for the clock portion of
the driver.
Also see these documents for generic binding information:
[1] Clock : ../clock/clock-bindings.txt
And these for relevant defines:
[2] include/dt-bindings/clock/lochnagar.h
This binding must be part of the Lochnagar MFD binding:
[3] ../mfd/cirrus,lochnagar.txt
Required properties:
- compatible : One of the following strings:
"cirrus,lochnagar1-clk"
"cirrus,lochnagar2-clk"
- #clock-cells : Must be 1. The first cell indicates the clock
number, see [2] for available clocks and [1].
Optional properties:
- clocks : Must contain an entry for each clock in clock-names.
- clock-names : May contain entries for each of the following
clocks:
- ln-cdc-clkout : Output clock from CODEC card.
- ln-dsp-clkout : Output clock from DSP card.
- ln-gf-mclk1,ln-gf-mclk2,ln-gf-mclk3,ln-gf-mclk4 : Optional
input audio clocks from host system.
- ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from
external connector.
- ln-spdif-mclk : Optional input audio clock from SPDIF.
- ln-spdif-clkout : Optional input audio clock from SPDIF.
- ln-adat-mclk : Optional input audio clock from ADAT.
- ln-pmic-32k : On board fixed clock.
- ln-clk-12m : On board fixed clock.
- ln-clk-11m : On board fixed clock.
- ln-clk-24m : On board fixed clock.
- ln-clk-22m : On board fixed clock.
- ln-clk-8m : On board fixed clock.
- ln-usb-clk-24m : On board fixed clock.
- ln-usb-clk-12m : On board fixed clock.
- assigned-clocks : A list of Lochnagar clocks to be reparented, see
[2] for available clocks.
- assigned-clock-parents : Parents to be assigned to the clocks
listed in "assigned-clocks".
Optional nodes:
- fixed-clock nodes may be registered for the following on board clocks:
- ln-pmic-32k : 32768 Hz
- ln-clk-12m : 12288000 Hz
- ln-clk-11m : 11298600 Hz
- ln-clk-24m : 24576000 Hz
- ln-clk-22m : 22579200 Hz
- ln-clk-8m : 8192000 Hz
- ln-usb-clk-24m : 24576000 Hz
- ln-usb-clk-12m : 12288000 Hz
Example:
lochnagar {
lochnagar-clk {
compatible = "cirrus,lochnagar2-clk";
#clock-cells = <1>;
clocks = <&clk-audio>, <&clk_pmic>;
clock-names = "ln-gf-mclk2", "ln-pmic-32k";
assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>,
<&lochnagar-clk LOCHNAGAR_CDC_MCLK2>;
assigned-clock-parents = <&clk-audio>,
<&clk-pmic>;
};
clk-pmic: clk-pmic {
compatible = "fixed-clock";
clock-cells = <0>;
clock-frequency = <32768>;
};
};
Documentation/devicetree/bindings/clock/cirrus,lochnagar.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic Lochnagar Audio Development Board
maintainers:
- patches@opensource.cirrus.com
description: |
Lochnagar is an evaluation and development board for Cirrus Logic
Smart CODEC and Amp devices. It allows the connection of most Cirrus
Logic devices on mini-cards, as well as allowing connection of various
application processor systems to provide a full evaluation platform.
Audio system topology, clocking and power can all be controlled through
the Lochnagar, allowing the device under test to be used in a variety of
possible use cases.
This binding document describes the binding for the clock portion of the
driver.
Also see these documents for generic binding information:
[1] Clock : ../clock/clock-bindings.txt
And these for relevant defines:
[2] include/dt-bindings/clock/lochnagar.h
This binding must be part of the Lochnagar MFD binding:
[3] ../mfd/cirrus,lochnagar.yaml
properties:
compatible:
enum:
- cirrus,lochnagar1-clk
- cirrus,lochnagar2-clk
'#clock-cells':
description:
The first cell indicates the clock number, see [2] for available
clocks and [1].
const: 1
clock-names:
items:
enum:
- ln-cdc-clkout # Output clock from CODEC card.
- ln-dsp-clkout # Output clock from DSP card.
- ln-gf-mclk1 # Optional input clock from host system.
- ln-gf-mclk2 # Optional input clock from host system.
- ln-gf-mclk3 # Optional input clock from host system.
- ln-gf-mclk4 # Optional input clock from host system.
- ln-psia1-mclk # Optional input clock from external connector.
- ln-psia2-mclk # Optional input clock from external connector.
- ln-spdif-mclk # Optional input clock from SPDIF.
- ln-spdif-clkout # Optional input clock from SPDIF.
- ln-adat-mclk # Optional input clock from ADAT.
- ln-pmic-32k # On board fixed clock.
- ln-clk-12m # On board fixed clock.
- ln-clk-11m # On board fixed clock.
- ln-clk-24m # On board fixed clock.
- ln-clk-22m # On board fixed clock.
- ln-clk-8m # On board fixed clock.
- ln-usb-clk-24m # On board fixed clock.
- ln-usb-clk-12m # On board fixed clock.
minItems: 1
maxItems: 19
clocks: true
assigned-clocks: true
assigned-clock-parents: true
additionalProperties: false
required:
- compatible
- '#clock-cells'
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
View file @ 571d54ed
......@@ -24,9 +24,8 @@ properties:
clock-div:
description: Fixed divider
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
clock-mult:
description: Fixed multiplier
......
Documentation/devicetree/bindings/clock/fsl,plldig.yaml
View file @ 571d54ed
......@@ -28,15 +28,14 @@ properties:
const: 0
fsl,vco-hz:
description: Optional for VCO frequency of the PLL in Hertz.
The VCO frequency of this PLL cannot be changed during runtime
only at startup. Therefore, the output frequencies are very
limited and might not even closely match the requested frequency.
To work around this restriction the user may specify its own
desired VCO frequency for the PLL.
minimum: 650000000
maximum: 1300000000
default: 1188000000
description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
of this PLL cannot be changed during runtime only at startup. Therefore,
the output frequencies are very limited and might not even closely match
the requested frequency. To work around this restriction the user may specify
its own desired VCO frequency for the PLL.
minimum: 650000000
maximum: 1300000000
default: 1188000000
required:
- compatible
......@@ -51,7 +50,7 @@ examples:
- |
dpclk: clock-display@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
reg = <0xf1f0000 0xffff>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
......
Documentation/devicetree/bindings/clock/imx1-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX1 CPUs
Required properties:
- compatible: Should be "fsl,imx1-ccm".
- reg: Address and length of the register set.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
Examples:
clks: ccm@21b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
pwm: pwm@208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx1-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX1 CPUs
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
properties:
compatible:
const: fsl,imx1-ccm
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx1-clock.h>
clock-controller@21b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
pwm@208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx21-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX21
Required properties:
- compatible : Should be "fsl,imx21-ccm".
- reg : Address and length of the register set.
- interrupts : Should contain CCM interrupt.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx21-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX21
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
properties:
compatible:
const: fsl,imx21-ccm
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx21-clock.h>
clock-controller@10027000 {
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
serial@1000a000 {
compatible = "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx23-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX23
Required properties:
- compatible: Should be "fsl,imx23-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX23
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll 1
ref_cpu 2
ref_emi 3
ref_pix 4
ref_io 5
saif_sel 6
lcdif_sel 7
gpmi_sel 8
ssp_sel 9
emi_sel 10
cpu 11
etm_sel 12
cpu_pll 13
cpu_xtal 14
hbus 15
xbus 16
lcdif_div 17
ssp_div 18
gpmi_div 19
emi_pll 20
emi_xtal 21
etm_div 22
saif_div 23
clk32k_div 24
rtc 25
adc 26
spdif_div 27
clk32k 28
dri 29
pwm 30
filt 31
uart 32
ssp 33
gpmi 34
spdif 35
emi 36
saif 37
lcdif 38
etm 39
usb 40
usb_phy 41
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
};
Documentation/devicetree/bindings/clock/imx23-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX23
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX23
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll 1
ref_cpu 2
ref_emi 3
ref_pix 4
ref_io 5
saif_sel 6
lcdif_sel 7
gpmi_sel 8
ssp_sel 9
emi_sel 10
cpu 11
etm_sel 12
cpu_pll 13
cpu_xtal 14
hbus 15
xbus 16
lcdif_div 17
ssp_div 18
gpmi_div 19
emi_pll 20
emi_xtal 21
etm_div 22
saif_div 23
clk32k_div 24
rtc 25
adc 26
spdif_div 27
clk32k 28
dri 29
pwm 30
filt 31
uart 32
ssp 33
gpmi 34
spdif 35
emi 36
saif 37
lcdif 38
etm 39
usb 40
usb_phy 41
properties:
compatible:
const: fsl,imx23-clkctrl
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@80040000 {
compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
};
Documentation/devicetree/bindings/clock/imx25-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX25
Required properties:
- compatible: Should be "fsl,imx25-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX25
clocks and IDs.
Clock ID
---------------------------
dummy 0
osc 1
mpll 2
upll 3
mpll_cpu_3_4 4
cpu_sel 5
cpu 6
ahb 7
usb_div 8
ipg 9
per0_sel 10
per1_sel 11
per2_sel 12
per3_sel 13
per4_sel 14
per5_sel 15
per6_sel 16
per7_sel 17
per8_sel 18
per9_sel 19
per10_sel 20
per11_sel 21
per12_sel 22
per13_sel 23
per14_sel 24
per15_sel 25
per0 26
per1 27
per2 28
per3 29
per4 30
per5 31
per6 32
per7 33
per8 34
per9 35
per10 36
per11 37
per12 38
per13 39
per14 40
per15 41
csi_ipg_per 42
epit_ipg_per 43
esai_ipg_per 44
esdhc1_ipg_per 45
esdhc2_ipg_per 46
gpt_ipg_per 47
i2c_ipg_per 48
lcdc_ipg_per 49
nfc_ipg_per 50
owire_ipg_per 51
pwm_ipg_per 52
sim1_ipg_per 53
sim2_ipg_per 54
ssi1_ipg_per 55
ssi2_ipg_per 56
uart_ipg_per 57
ata_ahb 58
reserved 59
csi_ahb 60
emi_ahb 61
esai_ahb 62
esdhc1_ahb 63
esdhc2_ahb 64
fec_ahb 65
lcdc_ahb 66
rtic_ahb 67
sdma_ahb 68
slcdc_ahb 69
usbotg_ahb 70
reserved 71
reserved 72
reserved 73
reserved 74
can1_ipg 75
can2_ipg 76
csi_ipg 77
cspi1_ipg 78
cspi2_ipg 79
cspi3_ipg 80
dryice_ipg 81
ect_ipg 82
epit1_ipg 83
epit2_ipg 84
reserved 85
esdhc1_ipg 86
esdhc2_ipg 87
fec_ipg 88
reserved 89
reserved 90
reserved 91
gpt1_ipg 92
gpt2_ipg 93
gpt3_ipg 94
gpt4_ipg 95
reserved 96
reserved 97
reserved 98
iim_ipg 99
reserved 100
reserved 101
kpp_ipg 102
lcdc_ipg 103
reserved 104
pwm1_ipg 105
pwm2_ipg 106
pwm3_ipg 107
pwm4_ipg 108
rngb_ipg 109
reserved 110
scc_ipg 111
sdma_ipg 112
sim1_ipg 113
sim2_ipg 114
slcdc_ipg 115
spba_ipg 116
ssi1_ipg 117
ssi2_ipg 118
tsc_ipg 119
uart1_ipg 120
uart2_ipg 121
uart3_ipg 122
uart4_ipg 123
uart5_ipg 124
reserved 125
wdt_ipg 126
cko_div 127
cko_sel 128
cko 129
Examples:
clks: ccm@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
};
uart1: serial@43f90000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx25-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX25
maintainers:
- Sascha Hauer <s.hauer@pengutronix.de>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX25
clocks and IDs.
Clock ID
--------------------------
dummy 0
osc 1
mpll 2
upll 3
mpll_cpu_3_4 4
cpu_sel 5
cpu 6
ahb 7
usb_div 8
ipg 9
per0_sel 10
per1_sel 11
per2_sel 12
per3_sel 13
per4_sel 14
per5_sel 15
per6_sel 16
per7_sel 17
per8_sel 18
per9_sel 19
per10_sel 20
per11_sel 21
per12_sel 22
per13_sel 23
per14_sel 24
per15_sel 25
per0 26
per1 27
per2 28
per3 29
per4 30
per5 31
per6 32
per7 33
per8 34
per9 35
per10 36
per11 37
per12 38
per13 39
per14 40
per15 41
csi_ipg_per 42
epit_ipg_per 43
esai_ipg_per 44
esdhc1_ipg_per 45
esdhc2_ipg_per 46
gpt_ipg_per 47
i2c_ipg_per 48
lcdc_ipg_per 49
nfc_ipg_per 50
owire_ipg_per 51
pwm_ipg_per 52
sim1_ipg_per 53
sim2_ipg_per 54
ssi1_ipg_per 55
ssi2_ipg_per 56
uart_ipg_per 57
ata_ahb 58
reserved 59
csi_ahb 60
emi_ahb 61
esai_ahb 62
esdhc1_ahb 63
esdhc2_ahb 64
fec_ahb 65
lcdc_ahb 66
rtic_ahb 67
sdma_ahb 68
slcdc_ahb 69
usbotg_ahb 70
reserved 71
reserved 72
reserved 73
reserved 74
can1_ipg 75
can2_ipg 76
csi_ipg 77
cspi1_ipg 78
cspi2_ipg 79
cspi3_ipg 80
dryice_ipg 81
ect_ipg 82
epit1_ipg 83
epit2_ipg 84
reserved 85
esdhc1_ipg 86
esdhc2_ipg 87
fec_ipg 88
reserved 89
reserved 90
reserved 91
gpt1_ipg 92
gpt2_ipg 93
gpt3_ipg 94
gpt4_ipg 95
reserved 96
reserved 97
reserved 98
iim_ipg 99
reserved 100
reserved 101
kpp_ipg 102
lcdc_ipg 103
reserved 104
pwm1_ipg 105
pwm2_ipg 106
pwm3_ipg 107
pwm4_ipg 108
rngb_ipg 109
reserved 110
scc_ipg 111
sdma_ipg 112
sim1_ipg 113
sim2_ipg 114
slcdc_ipg 115
spba_ipg 116
ssi1_ipg 117
ssi2_ipg 118
tsc_ipg 119
uart1_ipg 120
uart2_ipg 121
uart3_ipg 122
uart4_ipg 123
uart5_ipg 124
reserved 125
wdt_ipg 126
cko_div 127
cko_sel 128
cko 129
properties:
compatible:
const: fsl,imx25-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx25-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
serial@43f90000 {
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx27-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX27
Required properties:
- compatible: Should be "fsl,imx27-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx27-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx27-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX27
maintainers:
- Fabio Estevam <fabio.estevam@freescale.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
properties:
compatible:
const: fsl,imx27-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx27-clock.h>
clock-controller@10027000 {
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
interrupts = <31>;
#clock-cells = <1>;
};
serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx28-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX28
Required properties:
- compatible: Should be "fsl,imx28-clkctrl"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX28
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll0 1
pll1 2
pll2 3
ref_cpu 4
ref_emi 5
ref_io0 6
ref_io1 7
ref_pix 8
ref_hsadc 9
ref_gpmi 10
saif0_sel 11
saif1_sel 12
gpmi_sel 13
ssp0_sel 14
ssp1_sel 15
ssp2_sel 16
ssp3_sel 17
emi_sel 18
etm_sel 19
lcdif_sel 20
cpu 21
ptp_sel 22
cpu_pll 23
cpu_xtal 24
hbus 25
xbus 26
ssp0_div 27
ssp1_div 28
ssp2_div 29
ssp3_div 30
gpmi_div 31
emi_pll 32
emi_xtal 33
lcdif_div 34
etm_div 35
ptp 36
saif0_div 37
saif1_div 38
clk32k_div 39
rtc 40
lradc 41
spdif_div 42
clk32k 43
pwm 44
uart 45
ssp0 46
ssp1 47
ssp2 48
ssp3 49
gpmi 50
spdif 51
emi 52
saif0 53
saif1 54
lcdif 55
etm 56
fec 57
can0 58
can1 59
usb0 60
usb1 61
usb0_phy 62
usb1_phy 63
enet_out 64
Examples:
clks: clkctrl@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
};
Documentation/devicetree/bindings/clock/imx28-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX28
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX28
clocks and IDs.
Clock ID
------------------
ref_xtal 0
pll0 1
pll1 2
pll2 3
ref_cpu 4
ref_emi 5
ref_io0 6
ref_io1 7
ref_pix 8
ref_hsadc 9
ref_gpmi 10
saif0_sel 11
saif1_sel 12
gpmi_sel 13
ssp0_sel 14
ssp1_sel 15
ssp2_sel 16
ssp3_sel 17
emi_sel 18
etm_sel 19
lcdif_sel 20
cpu 21
ptp_sel 22
cpu_pll 23
cpu_xtal 24
hbus 25
xbus 26
ssp0_div 27
ssp1_div 28
ssp2_div 29
ssp3_div 30
gpmi_div 31
emi_pll 32
emi_xtal 33
lcdif_div 34
etm_div 35
ptp 36
saif0_div 37
saif1_div 38
clk32k_div 39
rtc 40
lradc 41
spdif_div 42
clk32k 43
pwm 44
uart 45
ssp0 46
ssp1 47
ssp2 48
ssp3 49
gpmi 50
spdif 51
emi 52
saif0 53
saif1 54
lcdif 55
etm 56
fec 57
can0 58
can1 59
usb0 60
usb1 61
usb0_phy 62
usb1_phy 63
enet_out 64
properties:
compatible:
const: fsl,imx28-clkctrl
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@80040000 {
compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
};
Documentation/devicetree/bindings/clock/imx31-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX31
Required properties:
- compatible: Should be "fsl,imx31-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX31
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
upll 5
mcu_main 6
hsp 7
ahb 8
nfc 9
ipg 10
per_div 11
per 12
csi_sel 13
fir_sel 14
csi_div 15
usb_div_pre 16
usb_div_post 17
fir_div_pre 18
fir_div_post 19
sdhc1_gate 20
sdhc2_gate 21
gpt_gate 22
epit1_gate 23
epit2_gate 24
iim_gate 25
ata_gate 26
sdma_gate 27
cspi3_gate 28
rng_gate 29
uart1_gate 30
uart2_gate 31
ssi1_gate 32
i2c1_gate 33
i2c2_gate 34
i2c3_gate 35
hantro_gate 36
mstick1_gate 37
mstick2_gate 38
csi_gate 39
rtc_gate 40
wdog_gate 41
pwm_gate 42
sim_gate 43
ect_gate 44
usb_gate 45
kpp_gate 46
ipu_gate 47
uart3_gate 48
uart4_gate 49
uart5_gate 50
owire_gate 51
ssi2_gate 52
cspi1_gate 53
cspi2_gate 54
gacc_gate 55
emi_gate 56
rtic_gate 57
firi_gate 58
Examples:
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>, <53>;
#clock-cells = <1>;
};
uart1: serial@43f90000 {
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx31-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX31
maintainers:
- Fabio Estevam <fabio.estevam@freescale.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX31
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
upll 5
mcu_main 6
hsp 7
ahb 8
nfc 9
ipg 10
per_div 11
per 12
csi_sel 13
fir_sel 14
csi_div 15
usb_div_pre 16
usb_div_post 17
fir_div_pre 18
fir_div_post 19
sdhc1_gate 20
sdhc2_gate 21
gpt_gate 22
epit1_gate 23
epit2_gate 24
iim_gate 25
ata_gate 26
sdma_gate 27
cspi3_gate 28
rng_gate 29
uart1_gate 30
uart2_gate 31
ssi1_gate 32
i2c1_gate 33
i2c2_gate 34
i2c3_gate 35
hantro_gate 36
mstick1_gate 37
mstick2_gate 38
csi_gate 39
rtc_gate 40
wdog_gate 41
pwm_gate 42
sim_gate 43
ect_gate 44
usb_gate 45
kpp_gate 46
ipu_gate 47
uart3_gate 48
uart4_gate 49
uart5_gate 50
owire_gate 51
ssi2_gate 52
cspi1_gate 53
cspi2_gate 54
gacc_gate 55
emi_gate 56
rtic_gate 57
firi_gate 58
properties:
compatible:
const: fsl,imx31-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for DVFS when a frequency change is requested, request 2 is
to generate interrupt for DPTC when a voltage change is requested.
items:
- description: CCM DVFS interrupt request 1
- description: CCM DPTC interrupt request 2
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>, <53>;
#clock-cells = <1>;
};
serial@43f90000 {
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
reg = <0x43f90000 0x4000>;
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx35-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX35
Required properties:
- compatible: Should be "fsl,imx35-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX35
clocks and IDs.
Clock ID
---------------------------
ckih 0
mpll 1
ppll 2
mpll_075 3
arm 4
hsp 5
hsp_div 6
hsp_sel 7
ahb 8
ipg 9
arm_per_div 10
ahb_per_div 11
ipg_per 12
uart_sel 13
uart_div 14
esdhc_sel 15
esdhc1_div 16
esdhc2_div 17
esdhc3_div 18
spdif_sel 19
spdif_div_pre 20
spdif_div_post 21
ssi_sel 22
ssi1_div_pre 23
ssi1_div_post 24
ssi2_div_pre 25
ssi2_div_post 26
usb_sel 27
usb_div 28
nfc_div 29
asrc_gate 30
pata_gate 31
audmux_gate 32
can1_gate 33
can2_gate 34
cspi1_gate 35
cspi2_gate 36
ect_gate 37
edio_gate 38
emi_gate 39
epit1_gate 40
epit2_gate 41
esai_gate 42
esdhc1_gate 43
esdhc2_gate 44
esdhc3_gate 45
fec_gate 46
gpio1_gate 47
gpio2_gate 48
gpio3_gate 49
gpt_gate 50
i2c1_gate 51
i2c2_gate 52
i2c3_gate 53
iomuxc_gate 54
ipu_gate 55
kpp_gate 56
mlb_gate 57
mshc_gate 58
owire_gate 59
pwm_gate 60
rngc_gate 61
rtc_gate 62
rtic_gate 63
scc_gate 64
sdma_gate 65
spba_gate 66
spdif_gate 67
ssi1_gate 68
ssi2_gate 69
uart1_gate 70
uart2_gate 71
uart3_gate 72
usbotg_gate 73
wdog_gate 74
max_gate 75
admux_gate 76
csi_gate 77
csi_div 78
csi_sel 79
iim_gate 80
gpu2d_gate 81
ckli_gate 82
Examples:
clks: ccm@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
esdhc1: esdhc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
clock-names = "ipg", "ahb", "per";
};
Documentation/devicetree/bindings/clock/imx35-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX35
maintainers:
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX35
clocks and IDs.
Clock ID
---------------------------
ckih 0
mpll 1
ppll 2
mpll_075 3
arm 4
hsp 5
hsp_div 6
hsp_sel 7
ahb 8
ipg 9
arm_per_div 10
ahb_per_div 11
ipg_per 12
uart_sel 13
uart_div 14
esdhc_sel 15
esdhc1_div 16
esdhc2_div 17
esdhc3_div 18
spdif_sel 19
spdif_div_pre 20
spdif_div_post 21
ssi_sel 22
ssi1_div_pre 23
ssi1_div_post 24
ssi2_div_pre 25
ssi2_div_post 26
usb_sel 27
usb_div 28
nfc_div 29
asrc_gate 30
pata_gate 31
audmux_gate 32
can1_gate 33
can2_gate 34
cspi1_gate 35
cspi2_gate 36
ect_gate 37
edio_gate 38
emi_gate 39
epit1_gate 40
epit2_gate 41
esai_gate 42
esdhc1_gate 43
esdhc2_gate 44
esdhc3_gate 45
fec_gate 46
gpio1_gate 47
gpio2_gate 48
gpio3_gate 49
gpt_gate 50
i2c1_gate 51
i2c2_gate 52
i2c3_gate 53
iomuxc_gate 54
ipu_gate 55
kpp_gate 56
mlb_gate 57
mshc_gate 58
owire_gate 59
pwm_gate 60
rngc_gate 61
rtc_gate 62
rtic_gate 63
scc_gate 64
sdma_gate 65
spba_gate 66
spdif_gate 67
ssi1_gate 68
ssi2_gate 69
uart1_gate 70
uart2_gate 71
uart3_gate 72
usbotg_gate 73
wdog_gate 74
max_gate 75
admux_gate 76
csi_gate 77
csi_div 78
csi_sel 79
iim_gate 80
gpu2d_gate 81
ckli_gate 82
properties:
compatible:
const: fsl,imx35-ccm
reg:
maxItems: 1
interrupts:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@53f80000 {
compatible = "fsl,imx35-ccm";
reg = <0x53f80000 0x4000>;
interrupts = <31>;
#clock-cells = <1>;
};
esdhc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
clock-names = "ipg", "ahb", "per";
};
Documentation/devicetree/bindings/clock/imx5-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX5
Required properties:
- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
for the full list of i.MX5 clock IDs.
Examples (for mx53):
clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx5-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX5
maintainers:
- Fabio Estevam <fabio.estevam@freescale.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
for the full list of i.MX5 clock IDs.
properties:
compatible:
enum:
- fsl,imx53-ccm
- fsl,imx51-ccm
- fsl,imx50-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
<0 72 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx6q-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX6 Quad
Required properties:
- compatible: Should be "fsl,imx6q-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
Optional properties:
- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
on power off.
Use this property if the SoC should be powered off by external power
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
be using "syscon-poweroff" driver instead.
- clocks: list of clock specifiers, must contain an entry for each entry
in clock-names
- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.
Examples:
#include <dt-bindings/clock/imx6qdl-clock.h>
clks: ccm@20c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
uart1: serial@2020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx6q-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX6 Quad
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
const: fsl,imx6q-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
maxItems: 2
'#clock-cells':
const: 1
clocks:
items:
- description: 24m osc
- description: 32k osc
- description: ckih1 clock input
- description: anaclk1 clock input
- description: anaclk2 clock input
clock-names:
items:
- const: osc
- const: ckil
- const: ckih1
- const: anaclk1
- const: anaclk2
fsl,pmic-stby-poweroff:
$ref: /schemas/types.yaml#/definitions/flag
description: |
Use this property if the SoC should be powered off by external power
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
be using "syscon-poweroff" driver instead.
required:
- compatible
- reg
- interrupts
- '#clock-cells'
examples:
# Clock Control Module node:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@20c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
<0 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/imx6sl-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX6 SoloLite
Required properties:
- compatible: Should be "fsl,imx6sl-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
for the full list of i.MX6 SoloLite clock IDs.
Documentation/devicetree/bindings/clock/imx6sl-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX6 SoloLite
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
const: fsl,imx6sl-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
maxItems: 2
'#clock-cells':
const: 1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
examples:
# Clock Control Module node:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@20c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
<0 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/imx6sll-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX6 SLL
Required properties:
- compatible: Should be "fsl,imx6sll-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
for the full list of i.MX6 SLL clock IDs.
Examples:
#include <dt-bindings/clock/imx6sll-clock.h>
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
};
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
<&clks IMX6SLL_CLK_UART1_SERIAL>;
clock-names = "ipg", "per";
};
Documentation/devicetree/bindings/clock/imx6sll-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX6 SLL
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
const: fsl,imx6sll-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
maxItems: 2
'#clock-cells':
const: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ipp_di0 clock input
- description: ipp_di1 clock input
clock-names:
items:
- const: ckil
- const: osc
- const: ipp_di0
- const: ipp_di1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
- clocks
- clock-names
examples:
# Clock Control Module node:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
};
Documentation/devicetree/bindings/clock/imx6sx-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX6 SoloX
Required properties:
- compatible: Should be "fsl,imx6sx-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
for the full list of i.MX6 SoloX clock IDs.
Documentation/devicetree/bindings/clock/imx6sx-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX6 SoloX
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
const: fsl,imx6sx-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
maxItems: 2
'#clock-cells':
const: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ipp_di0 clock input
- description: ipp_di1 clock input
- description: anaclk1 clock input
- description: anaclk2 clock input
clock-names:
items:
- const: ckil
- const: osc
- const: ipp_di0
- const: ipp_di1
- const: anaclk1
- const: anaclk2
required:
- compatible
- reg
- interrupts
- '#clock-cells'
- clocks
- clock-names
examples:
# Clock Control Module node:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@20c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
};
Documentation/devicetree/bindings/clock/imx6ul-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX6 UltraLite
Required properties:
- compatible: Should be "fsl,imx6ul-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
for the full list of i.MX6 UltraLite clock IDs.
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX6 UltraLite
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
const: fsl,imx6ul-ccm
reg:
maxItems: 1
interrupts:
description: CCM provides 2 interrupt requests, request 1 is to generate
interrupt for frequency or mux change, request 2 is to generate
interrupt for oscillator read or PLL lock.
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
maxItems: 2
'#clock-cells':
const: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ipp_di0 clock input
- description: ipp_di1 clock input
clock-names:
items:
- const: ckil
- const: osc
- const: ipp_di0
- const: ipp_di1
required:
- compatible
- reg
- interrupts
- '#clock-cells'
- clocks
- clock-names
examples:
# Clock Control Module node:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@20c4000 {
compatible = "fsl,imx6ul-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
};
Documentation/devicetree/bindings/clock/imx7d-clock.txt deleted 100644 → 0
View file @ 9d71d3cd
* Clock bindings for Freescale i.MX7 Dual
Required properties:
- compatible: Should be "fsl,imx7d-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
for the full list of i.MX7 Dual clock IDs.
Documentation/devicetree/bindings/clock/imx7d-clock.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX7 Dual
maintainers:
- Frank Li <Frank.Li@nxp.com>
- Anson Huang <Anson.Huang@nxp.com>
description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
for the full list of i.MX7 Dual clock IDs.
properties:
compatible:
const: fsl,imx7d-ccm
reg:
maxItems: 1
interrupts:
items:
- description: CCM interrupt request 1
- description: CCM interrupt request 2
'#clock-cells':
const: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
clock-names:
items:
- const: ckil
- const: osc
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@30380000 {
compatible = "fsl,imx7d-ccm";
reg = <0x30380000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>;
clock-names = "ckil", "osc";
};
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt deleted 100644 → 0
View file @ 9d71d3cd
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
Note:
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
Required properties:
- compatible: Should be one of:
"fsl,imx8qxp-lpcg-adma",
"fsl,imx8qxp-lpcg-conn",
"fsl,imx8qxp-lpcg-dc",
"fsl,imx8qxp-lpcg-dsp",
"fsl,imx8qxp-lpcg-gpu",
"fsl,imx8qxp-lpcg-hsio",
"fsl,imx8qxp-lpcg-img",
"fsl,imx8qxp-lpcg-lsio",
"fsl,imx8qxp-lpcg-vpu"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See the full list of clock IDs from:
include/dt-bindings/clock/imx8qxp-clock.h
Examples:
#include <dt-bindings/clock/imx8qxp-clock.h>
conn_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
usdhc1: mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
};
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
maintainers:
- Aisheng Dong <aisheng.dong@nxp.com>
description: |
The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
This level of clock gating is provided after the clocks are generated
by the SCU resources and clock controls. Thus even if the clock is
enabled by these control bits, it might still not be running based
on the base resource.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from:
include/dt-bindings/clock/imx8-clock.h
properties:
compatible:
enum:
- fsl,imx8qxp-lpcg-adma
- fsl,imx8qxp-lpcg-conn
- fsl,imx8qxp-lpcg-dc
- fsl,imx8qxp-lpcg-dsp
- fsl,imx8qxp-lpcg-gpu
- fsl,imx8qxp-lpcg-hsio
- fsl,imx8qxp-lpcg-img
- fsl,imx8qxp-lpcg-lsio
- fsl,imx8qxp-lpcg-vpu
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
#clock-cells = <1>;
};
mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
Documentation/devicetree/bindings/clock/ingenic,cgu.txt deleted 100644 → 0
View file @ 9d71d3cd
Ingenic SoC CGU binding
The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
typically includes a variety of PLLs, multiplexers, dividers & gates in order
to provide many different clock signals derived from only 2 external source
clocks.
Required properties:
- compatible : Should be one of:
* ingenic,jz4740-cgu
* ingenic,jz4725b-cgu
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
* ingenic,x1000-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal
"ext" and second the RTC clock source "rtc".
- clock-names : List of name strings for the external clocks.
- #clock-cells: Should be 1.
Clock consumers specify this argument to identify a clock. The valid values
may be found in <dt-bindings/clock/<soctype>-cgu.h>.
Example SoC include file:
/ {
cgu: jz4740-cgu {
compatible = "ingenic,jz4740-cgu";
reg = <0x10000000 0x100>;
#clock-cells = <1>;
};
uart0: serial@10030000 {
clocks = <&cgu JZ4740_CLK_UART0>;
};
};
Example board file:
/ {
ext: clock@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
rtc: clock@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
&cgu {
clocks = <&ext> <&rtc>;
clock-names: "ext", "rtc";
};
};
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs CGU devicetree bindings
description: |
The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
typically includes a variety of PLLs, multiplexers, dividers & gates in order
to provide many different clock signals derived from only 2 external source
clocks.
maintainers:
- Paul Cercueil <paul@crapouillou.net>
select:
properties:
compatible:
contains:
enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
- ingenic,x1830-cgu
required:
- compatible
properties:
$nodename:
pattern: "^clock-controller@[0-9a-f]+$"
"#address-cells":
const: 1
"#size-cells":
const: 1
"#clock-cells":
const: 1
ranges: true
compatible:
items:
- enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
- ingenic,x1830-cgu
- const: simple-mfd
minItems: 1
reg:
maxItems: 1
clocks:
items:
- description: External oscillator clock
- description: Internal 32 kHz RTC clock
clock-names:
items:
- const: ext
- enum:
- rtc
- osc32k # Different name, same clock
assigned-clocks:
minItems: 1
maxItems: 64
assigned-clock-parents:
minItems: 1
maxItems: 64
assigned-clock-rates:
minItems: 1
maxItems: 64
required:
- "#clock-cells"
- compatible
- reg
- clocks
- clock-names
patternProperties:
"^usb-phy@[a-f0-9]+$":
allOf: [ $ref: "../usb/ingenic,jz4770-phy.yaml#" ]
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4770-cgu.h>
cgu: clock-controller@10000000 {
compatible = "ingenic,jz4770-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000000 0x100>;
clocks = <&ext>, <&osc32k>;
clock-names = "ext", "osc32k";
#clock-cells = <1>;
otg_phy: usb-phy@3c {
compatible = "ingenic,jz4770-phy";
reg = <0x3c 0x10>;
clocks = <&cgu JZ4770_CLK_OTG_PHY>;
vcc-supply = <&ldo5>;
#phy-cells = <0>;
};
};
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View file @ 571d54ed
......@@ -65,7 +65,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7180";
reg = <0 0x00100000 0 0x1f0000>;
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View file @ 571d54ed
......@@ -63,7 +63,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8150";
reg = <0 0x00100000 0 0x1f0000>;
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View file @ 571d54ed
......@@ -61,7 +61,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sm8250";
reg = <0 0x00100000 0 0x1f0000>;
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
......
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View file @ 571d54ed
......@@ -15,15 +15,15 @@ description: |
power domains.
properties:
compatible :
compatible:
enum:
- qcom,mmcc-apq8064
- qcom,mmcc-apq8084
- qcom,mmcc-msm8660
- qcom,mmcc-msm8960
- qcom,mmcc-msm8974
- qcom,mmcc-msm8996
- qcom,mmcc-msm8998
- qcom,mmcc-apq8064
- qcom,mmcc-apq8084
- qcom,mmcc-msm8660
- qcom,mmcc-msm8960
- qcom,mmcc-msm8974
- qcom,mmcc-msm8996
- qcom,mmcc-msm8998
clocks:
items:
......
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
View file @ 571d54ed
......@@ -66,7 +66,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@af00000 {
compatible = "qcom,sc7180-dispcc";
reg = <0 0x0af00000 0 0x200000>;
reg = <0x0af00000 0x200000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
......
Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
View file @ 571d54ed
......@@ -60,7 +60,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@5090000 {
compatible = "qcom,sc7180-gpucc";
reg = <0 0x05090000 0 0x9000>;
reg = <0x05090000 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
......
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
View file @ 571d54ed
......@@ -50,7 +50,7 @@ examples:
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
clock-controller@41a8000 {
compatible = "qcom,sc7180-mss";
reg = <0 0x041a8000 0 0x8000>;
reg = <0x041a8000 0x8000>;
clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&gcc GCC_MSS_NAV_AXI_CLK>,
<&gcc GCC_MSS_CFG_AHB_CLK>;
......
Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
View file @ 571d54ed
......@@ -55,7 +55,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ab00000 {
compatible = "qcom,sc7180-videocc";
reg = <0 0x0ab00000 0 0x10000>;
reg = <0x0ab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
......
Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
View file @ 571d54ed
......@@ -75,7 +75,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0 0x0af00000 0 0x10000>;
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
......
Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
View file @ 571d54ed
......@@ -60,7 +60,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0 0x05090000 0 0x9000>;
reg = <0x05090000 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
......
Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
View file @ 571d54ed
......@@ -55,7 +55,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0 0x0ab00000 0 0x10000>;
reg = <0x0ab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
......
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
View file @ 571d54ed
......@@ -76,29 +76,24 @@ examples:
- |
ap_clk: clock-controller@21500000 {
compatible = "sprd,sc9863a-ap-clk";
reg = <0 0x21500000 0 0x1000>;
reg = <0x21500000 0x1000>;
clocks = <&ext_26m>, <&ext_32k>;
clock-names = "ext-26m", "ext-32k";
#clock-cells = <1>;
};
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
ap_ahb_regs: syscon@20e00000 {
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
reg = <0 0x20e00000 0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x20e00000 0x4000>;
apahb_gate: apahb-gate@0 {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
};
syscon@20e00000 {
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
reg = <0x20e00000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x20e00000 0x4000>;
apahb_gate: apahb-gate@0 {
compatible = "sprd,sc9863a-apahb-gate";
reg = <0x0 0x1020>;
#clock-cells = <1>;
};
};
......
Documentation/devicetree/bindings/connector/usb-connector.yaml
View file @ 571d54ed
......@@ -15,10 +15,15 @@ description:
properties:
compatible:
enum:
- usb-a-connector
- usb-b-connector
- usb-c-connector
oneOf:
- enum:
- usb-a-connector
- usb-b-connector
- usb-c-connector
- items:
- const: gpio-usb-b-connector
- const: usb-b-connector
label:
description: Symbolic name for the connector.
......@@ -27,8 +32,8 @@ properties:
description: Size of the connector, should be specified in case of
non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
connectors.
allOf:
- $ref: /schemas/types.yaml#definitions/string
$ref: /schemas/types.yaml#definitions/string
enum:
- mini
- micro
......@@ -57,8 +62,8 @@ properties:
power-role:
description: Determines the power role that the Type C connector will
support. "dual" refers to Dual Role Port (DRP).
allOf:
- $ref: /schemas/types.yaml#definitions/string
$ref: /schemas/types.yaml#definitions/string
enum:
- source
- sink
......@@ -66,18 +71,18 @@ properties:
try-power-role:
description: Preferred power role.
allOf:
- $ref: /schemas/types.yaml#definitions/string
$ref: /schemas/types.yaml#definitions/string
enum:
- source
- sink
- dual
- source
- sink
- dual
data-role:
description: Data role if Type C connector supports USB data. "dual" refers
Dual Role Device (DRD).
allOf:
- $ref: /schemas/types.yaml#definitions/string
$ref: /schemas/types.yaml#definitions/string
enum:
- host
- device
......@@ -95,8 +100,7 @@ properties:
defined in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
sink-pdos:
description: An array of u32 with each entry providing supported power sink
......@@ -108,8 +112,7 @@ properties:
in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
op-sink-microwatt:
description: Sink required operating power in microwatt, if source can't
......@@ -142,9 +145,22 @@ properties:
required:
- compatible
allOf:
- if:
properties:
compatible:
contains:
const: gpio-usb-b-connector
then:
anyOf:
- required:
- vbus-gpios
- required:
- id-gpios
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
- |+
- |
muic-max77843 {
usb_con1: connector {
compatible = "usb-b-connector";
......@@ -156,7 +172,7 @@ examples:
# USB-C connector attached to CC controller (s2mm005), HS lines routed
# to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
# DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
- |+
- |
ccic: s2mm005 {
usb_con2: connector {
compatible = "usb-c-connector";
......@@ -190,7 +206,7 @@ examples:
# USB-C connector attached to a typec port controller(ptn5110), which has
# power delivery support and enables drp.
- |+
- |
#include <dt-bindings/usb/pd.h>
typec: ptn5110 {
usb_con3: connector {
......@@ -204,3 +220,16 @@ examples:
op-sink-microwatt = <10000000>;
};
};
# USB connector with GPIO control lines
- |
#include <dt-bindings/gpio/gpio.h>
usb {
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
vbus-supply = <&usb_p0_vbus>;
};
};
Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml
View file @ 571d54ed
......@@ -15,16 +15,16 @@ properties:
oneOf:
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun5i-a13-crypto
- const: allwinner,sun4i-a10-crypto
- const: allwinner,sun5i-a13-crypto
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun6i-a31-crypto
- const: allwinner,sun4i-a10-crypto
- const: allwinner,sun6i-a31-crypto
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun7i-a20-crypto
- const: allwinner,sun4i-a10-crypto
- const: allwinner,sun7i-a20-crypto
- const: allwinner,sun4i-a10-crypto
- items:
- const: allwinner,sun8i-a33-crypto
- const: allwinner,sun8i-a33-crypto
reg:
maxItems: 1
......
Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
View file @ 571d54ed
......@@ -50,16 +50,16 @@ if:
const: allwinner,sun50i-h6-crypto
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
clocks:
minItems: 3
clock-names:
minItems: 3
else:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
clocks:
maxItems: 2
clock-names:
maxItems: 2
required:
- compatible
......
Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml
View file @ 571d54ed
......@@ -12,7 +12,7 @@ maintainers:
properties:
compatible:
items:
- const: amlogic,gxl-crypto
- const: amlogic,gxl-crypto
reg:
maxItems: 1
......@@ -45,7 +45,7 @@ examples:
crypto: crypto-engine@c883e000 {
compatible = "amlogic,gxl-crypto";
reg = <0x0 0xc883e000 0x0 0x36>;
reg = <0xc883e000 0x36>;
interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_BLKMV>;
clock-names = "blkmv";
......
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
View file @ 571d54ed
......@@ -36,11 +36,10 @@ properties:
dma-maxburst:
description: Set number of maximum dma burst supported
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 2
- default: 0
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2
default: 0
required:
- compatible
......
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
View file @ 571d54ed
......@@ -66,10 +66,9 @@ properties:
- allwinner,sun50i-h6-display-engine
allwinner,pipelines:
allOf:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- minItems: 1
maxItems: 2
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
description: |
Available display engine frontends (DE 1.0) or mixers (DE
2.0/3.0) available.
......
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-hdmi.yaml
View file @ 571d54ed
......@@ -21,8 +21,8 @@ properties:
- const: allwinner,sun5i-a10s-hdmi
- const: allwinner,sun6i-a31-hdmi
- items:
- const: allwinner,sun7i-a20-hdmi
- const: allwinner,sun5i-a10s-hdmi
- const: allwinner,sun7i-a20-hdmi
- const: allwinner,sun5i-a10s-hdmi
reg:
maxItems: 1
......@@ -33,32 +33,32 @@ properties:
clocks:
oneOf:
- items:
- description: The HDMI interface clock
- description: The HDMI module clock
- description: The first video PLL
- description: The second video PLL
- description: The HDMI interface clock
- description: The HDMI module clock
- description: The first video PLL
- description: The second video PLL
- items:
- description: The HDMI interface clock
- description: The HDMI module clock
- description: The HDMI DDC clock
- description: The first video PLL
- description: The second video PLL
- description: The HDMI interface clock
- description: The HDMI module clock
- description: The HDMI DDC clock
- description: The first video PLL
- description: The second video PLL
clock-names:
oneOf:
- items:
- const: ahb
- const: mod
- const: pll-0
- const: pll-1
- const: ahb
- const: mod
- const: pll-0
- const: pll-1
- items:
- const: ahb
- const: mod
- const: ddc
- const: pll-0
- const: pll-1
- const: ahb
- const: mod
- const: ddc
- const: pll-0
- const: pll-1
resets:
maxItems: 1
......
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
View file @ 571d54ed
......@@ -35,26 +35,26 @@ properties:
- const: allwinner,sun9i-a80-tcon-tv
- items:
- enum:
- allwinner,sun7i-a20-tcon0
- allwinner,sun7i-a20-tcon1
- const: allwinner,sun7i-a20-tcon
- enum:
- allwinner,sun7i-a20-tcon0
- allwinner,sun7i-a20-tcon1
- const: allwinner,sun7i-a20-tcon
- items:
- enum:
- allwinner,sun50i-a64-tcon-lcd
- const: allwinner,sun8i-a83t-tcon-lcd
- enum:
- allwinner,sun50i-a64-tcon-lcd
- const: allwinner,sun8i-a83t-tcon-lcd
- items:
- enum:
- allwinner,sun8i-h3-tcon-tv
- allwinner,sun50i-a64-tcon-tv
- const: allwinner,sun8i-a83t-tcon-tv
- enum:
- allwinner,sun8i-h3-tcon-tv
- allwinner,sun50i-a64-tcon-tv
- const: allwinner,sun8i-a83t-tcon-tv
- items:
- enum:
- allwinner,sun50i-h6-tcon-tv
- const: allwinner,sun8i-r40-tcon-tv
- enum:
- allwinner,sun50i-h6-tcon-tv
- const: allwinner,sun8i-r40-tcon-tv
reg:
maxItems: 1
......@@ -71,11 +71,10 @@ properties:
maxItems: 4
clock-output-names:
allOf:
- $ref: /schemas/types.yaml#/definitions/string-array
- maxItems: 1
description:
Name of the LCD pixel clock created.
$ref: /schemas/types.yaml#/definitions/string-array
maxItems: 1
dmas:
maxItems: 1
......@@ -83,37 +82,37 @@ properties:
resets:
anyOf:
- items:
- description: TCON Reset Line
- description: TCON Reset Line
- items:
- description: TCON Reset Line
- description: TCON LVDS Reset Line
- description: TCON Reset Line
- description: TCON LVDS Reset Line
- items:
- description: TCON Reset Line
- description: TCON eDP Reset Line
- description: TCON Reset Line
- description: TCON eDP Reset Line
- items:
- description: TCON Reset Line
- description: TCON eDP Reset Line
- description: TCON LVDS Reset Line
- description: TCON Reset Line
- description: TCON eDP Reset Line
- description: TCON LVDS Reset Line
reset-names:
oneOf:
- const: lcd
- items:
- const: lcd
- const: lvds
- const: lcd
- const: lvds
- items:
- const: lcd
- const: edp
- const: lcd
- const: edp
- items:
- const: lcd
- const: edp
- const: lvds
- const: lcd
- const: edp
- const: lvds
ports:
type: object
......
Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
View file @ 571d54ed
......@@ -76,28 +76,28 @@ required:
allOf:
- if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-mipi-dsi
compatible:
contains:
const: allwinner,sun6i-a31-mipi-dsi
then:
properties:
clocks:
minItems: 2
properties:
clocks:
minItems: 2
required:
- clock-names
required:
- clock-names
- if:
properties:
compatible:
contains:
const: allwinner,sun50i-a64-mipi-dsi
compatible:
contains:
const: allwinner,sun50i-a64-mipi-dsi
then:
properties:
clocks:
minItems: 1
properties:
clocks:
minItems: 1
additionalProperties: false
......
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
View file @ 571d54ed
......@@ -29,11 +29,11 @@ properties:
- const: allwinner,sun50i-h6-dw-hdmi
- items:
- enum:
- allwinner,sun8i-h3-dw-hdmi
- allwinner,sun8i-r40-dw-hdmi
- allwinner,sun50i-a64-dw-hdmi
- const: allwinner,sun8i-a83t-dw-hdmi
- enum:
- allwinner,sun8i-h3-dw-hdmi
- allwinner,sun8i-r40-dw-hdmi
- allwinner,sun50i-a64-dw-hdmi
- const: allwinner,sun8i-a83t-dw-hdmi
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml 0 → 100644
View file @ 571d54ed
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/analogix,anx7814.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
maintainers:
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
properties:
compatible:
enum:
- analogix,anx7808
- analogix,anx7812
- analogix,anx7814
- analogix,anx7818
reg:
maxItems: 1
description: I2C address of the device.
interrupts:
maxItems: 1
description: Should contain the INTP interrupt.
hpd-gpios:
deprecated: true
maxItems: 1
description: Which GPIO to use for hpd.
pd-gpios:
maxItems: 1
description: Which GPIO to use for power down.
reset-gpios:
maxItems: 1
description: Which GPIO to use for reset.
dvdd10-supply:
description: Regulator for 1.0V digital core power.
ports:
type: object
description:
A node containing input and output port nodes with endpoint
definitions as documented in
Documentation/devicetree/bindings/media/video-interfaces.txt
Documentation/devicetree/bindings/graph.txt
properties:
port@0:
type: object
description: Video port for HDMI input.
properties:
reg:
const: 0
port@1:
type: object
description:
Video port for SlimPort, DisplayPort, eDP or MyDP output.
properties:
reg:
const: 1
required:
- port@0
- port@1
required:
- compatible
- reg
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
anx7814: bridge@38 {
compatible = "analogix,anx7814";
reg = <0x38>;
interrupt-parent = <&gpio0>;
interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */
pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
anx7814_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
port@1 {
reg = <1>;
anx7814_out: endpoint {
remote-endpoint = <&edp_out>;
};
};
};
};
};
...
Documentation/devicetree/bindings/display/bridge/anx7814.txt deleted 100644 → 0
View file @ 9d71d3cd
Analogix ANX7814 SlimPort (Full-HD Transmitter)
-----------------------------------------------
The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter
designed for portable devices.
Required properties:
- compatible : Must be one of:
"analogix,anx7808"
"analogix,anx7812"
"analogix,anx7814"
"analogix,anx7818"
- reg : I2C address of the device
- interrupts : Should contain the INTP interrupt
- hpd-gpios : Which GPIO to use for hpd
- pd-gpios : Which GPIO to use for power down
- reset-gpios : Which GPIO to use for reset
Optional properties:
- dvdd10-supply : Regulator for 1.0V digital core power.
- Video port for HDMI input, using the DT bindings defined in [1].
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
anx7814: anx7814@38 {
compatible = "analogix,anx7814";
reg = <0x38>;
interrupt-parent = <&gpio0>;
interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */
hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
port {
anx7814_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
};
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
View file @ 571d54ed
......@@ -32,17 +32,17 @@ properties:
compatible:
oneOf:
- items:
- enum:
- ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer
- ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer
- ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
- const: lvds-encoder # Generic LVDS encoder compatible fallback
- enum:
- ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer
- ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer
- ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
- const: lvds-encoder # Generic LVDS encoder compatible fallback
- items:
- enum:
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:
- thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
- thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
ports:
type: object
......
Documentation/devicetree/bindings/display/panel/panel-common.yaml
View file @ 571d54ed
......@@ -48,9 +48,8 @@ properties:
rotation:
description:
Display rotation in degrees counter clockwise (0,90,180,270)
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 90, 180, 270 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 90, 180, 270]
# Display Timings
panel-timing:
......@@ -58,16 +57,14 @@ properties:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
timings.
allOf:
- $ref: panel-timing.yaml#
$ref: panel-timing.yaml#
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
allOf:
- $ref: display-timings.yaml#
$ref: display-timings.yaml#
# Connectivity
port:
......
Documentation/devicetree/bindings/display/panel/panel-timing.yaml
View file @ 571d54ed
......@@ -72,92 +72,80 @@ properties:
hfront-porch:
description: Horizontal front porch panel timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of pixels
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
hback-porch:
description: Horizontal back porch timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of pixels
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
hsync-len:
description: Horizontal sync length panel timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of pixels
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of pixels
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of pixels
vfront-porch:
description: Vertical front porch panel timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of lines
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
vback-porch:
description: Vertical back porch panel timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of lines
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
vsync-len:
description: Vertical sync length panel timing
oneOf:
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- maxItems: 1
items:
description: typical number of lines
- allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
- $ref: /schemas/types.yaml#/definitions/uint32
maxItems: 1
items:
description: typical number of lines
- $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
description: min, typ, max number of lines
hsync-active:
description: |
......
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