Commit 585cf175 authored by Tzachi Perelstein's avatar Tzachi Perelstein Committed by Russell King

[ARM] basic support for the Marvell Orion SoC family

The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.

This contains the basic structure and architecture register definitions.
Signed-off-by: default avatarTzachi Perelstein <tzachi@marvell.com>
Reviewed-by: default avatarNicolas Pitre <nico@marvell.com>
Reviewed-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Acked-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d910a0aa
...@@ -333,6 +333,12 @@ config ARCH_MXC ...@@ -333,6 +333,12 @@ config ARCH_MXC
help help
Support for Freescale MXC/iMX-based family of processors Support for Freescale MXC/iMX-based family of processors
config ARCH_ORION
bool "Marvell Orion"
depends on MMU
help
Support for Marvell Orion System on Chip family.
config ARCH_PNX4008 config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile" bool "Philips Nexperia PNX4008 Mobile"
help help
...@@ -441,6 +447,8 @@ source "arch/arm/mach-omap1/Kconfig" ...@@ -441,6 +447,8 @@ source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig" source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig" source "arch/arm/plat-s3c/Kconfig"
......
...@@ -139,6 +139,7 @@ endif ...@@ -139,6 +139,7 @@ endif
machine-$(CONFIG_ARCH_KS8695) := ks8695 machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_ORION) := orion
ifeq ($(CONFIG_ARCH_EBSA110),y) ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line. # This is what happens if you forget the IOCS16 line.
......
if ARCH_ORION
menu "Orion Implementations"
endmenu
endif
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
/*
* arch/arm/mach-orion/common.c
*
* Core functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/arch/orion.h>
#include "common.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
{
.virtual = ORION_REGS_BASE,
.pfn = __phys_to_pfn(ORION_REGS_BASE),
.length = ORION_REGS_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
.length = ORION_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCI_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
.length = ORION_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_WA_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
.length = ORION_PCIE_WA_SIZE,
.type = MT_DEVICE
},
};
void __init orion_map_io(void)
{
iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
}
#ifndef __ARCH_ORION_COMMON_H__
#define __ARCH_ORION_COMMON_H__
/*
* Basic Orion init functions used early by machine-setup.
*/
void __init orion_map_io(void);
#endif /* __ARCH_ORION_COMMON_H__ */
/*
* linux/include/asm-arm/arch-orion/debug-macro.S
*
* Debugging macro include header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart,rx
mov \rx, #0xf1000000
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>
/*
* include/asm-arm/arch-orion/entry-macro.S
*
* Low-level IRQ helper macros for Orion platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/orion.h>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =MAIN_IRQ_CAUSE
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #0] @ main cause
ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
mov \irqnr, #0 @ default irqnr
@ find cause bits that are unmasked
ands \irqstat, \irqstat, \tmp @ clear Z flag if any
clzne \irqnr, \irqstat @ calc irqnr
rsbne \irqnr, \irqnr, #31
.endm
/*
* include/asm-arm/arch-orion/hardware.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
#include "orion.h"
#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
#endif /* _ASM_ARCH_HARDWARE_H */
/*
* include/asm-arm/arch-orion/io.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include "orion.h"
#define IO_SPACE_LIMIT 0xffffffff
#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)addr;
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#endif
/*
* include/asm-arm/arch-orion/irqs.h
*
* IRQ definitions for Orion SoC
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_IRQS_H__
#define __ASM_ARCH_IRQS_H__
#include "orion.h" /* need GPIO_MAX */
/*
* Orion Main Interrupt Controller
*/
#define IRQ_ORION_BRIDGE 0
#define IRQ_ORION_DOORBELL_H2C 1
#define IRQ_ORION_DOORBELL_C2H 2
#define IRQ_ORION_UART0 3
#define IRQ_ORION_UART1 4
#define IRQ_ORION_I2C 5
#define IRQ_ORION_GPIO_0_7 6
#define IRQ_ORION_GPIO_8_15 7
#define IRQ_ORION_GPIO_16_23 8
#define IRQ_ORION_GPIO_24_31 9
#define IRQ_ORION_PCIE0_ERR 10
#define IRQ_ORION_PCIE0_INT 11
#define IRQ_ORION_USB1_CTRL 12
#define IRQ_ORION_DEV_BUS_ERR 14
#define IRQ_ORION_PCI_ERR 15
#define IRQ_ORION_USB_BR_ERR 16
#define IRQ_ORION_USB0_CTRL 17
#define IRQ_ORION_ETH_RX 18
#define IRQ_ORION_ETH_TX 19
#define IRQ_ORION_ETH_MISC 20
#define IRQ_ORION_ETH_SUM 21
#define IRQ_ORION_ETH_ERR 22
#define IRQ_ORION_IDMA_ERR 23
#define IRQ_ORION_IDMA_0 24
#define IRQ_ORION_IDMA_1 25
#define IRQ_ORION_IDMA_2 26
#define IRQ_ORION_IDMA_3 27
#define IRQ_ORION_CESA 28
#define IRQ_ORION_SATA 29
#define IRQ_ORION_XOR0 30
#define IRQ_ORION_XOR1 31
/*
* Orion General Purpose Pins
*/
#define IRQ_ORION_GPIO_START 32
#define NR_GPIO_IRQS GPIO_MAX
#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
#endif /* __ASM_ARCH_IRQS_H__ */
/*
* include/asm-arm/arch-orion/memory.h
*
* Marvell Orion memory definitions
*/
#ifndef __ASM_ARCH_MMU_H
#define __ASM_ARCH_MMU_H
#define PHYS_OFFSET UL(0x00000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
/*
* include/asm-arm/arch-orion/orion.h
*
* Generic definitions of Orion SoC flavors:
* Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
*
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_ORION_H__
#define __ASM_ARCH_ORION_H__
/*******************************************************************************
* Orion Address Map
* Use the same mapping (1:1 virtual:physical) of internal registers and
* PCI system (PCI+PCIE) for all machines.
* Each machine defines the rest of its mapping (e.g. device bus flashes)
******************************************************************************/
#define ORION_REGS_BASE 0xf1000000
#define ORION_REGS_SIZE SZ_1M
#define ORION_PCI_SYS_MEM_BASE 0xe0000000
#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
#define ORION_PCIE_MEM_SIZE SZ_128M
#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
#define ORION_PCI_MEM_SIZE SZ_128M
#define ORION_PCI_SYS_IO_BASE 0xf2000000
#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
#define ORION_PCIE_IO_SIZE SZ_1M
#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
#define ORION_PCI_IO_SIZE SZ_1M
#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
/* Relevant only for Orion-NAS */
#define ORION_PCIE_WA_BASE 0xf0000000
#define ORION_PCIE_WA_SIZE SZ_16M
/*******************************************************************************
* Supported Devices & Revisions
******************************************************************************/
/* Orion-NAS (88F5182) */
#define MV88F5182_DEV_ID 0x5182
#define MV88F5182_REV_A2 2
/* Orion-2 (88F5281) */
#define MV88F5281_DEV_ID 0x5281
#define MV88F5281_REV_D1 5
#define MV88F5281_REV_D2 6
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
/*******************************************************************************
* Device Bus Registers
******************************************************************************/
#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
#define GPIO_MAX 32
/***************************************************************************
* Orion CPU Bridge Registers
**************************************************************************/
#define CPU_CONF ORION_BRIDGE_REG(0x100)
#define CPU_CTRL ORION_BRIDGE_REG(0x104)
#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
#ifndef __ASSEMBLY__
/*******************************************************************************
* Helpers to access Orion registers
******************************************************************************/
#include <asm/types.h>
#include <asm/io.h>
#define orion_read(r) __raw_readl(r)
#define orion_write(r, val) __raw_writel(val, r)
/*
* These are not preempt safe. Locks, if needed, must be taken care by caller.
*/
#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_ORION_H__ */
/*
* include/asm-arm/arch-orion/system.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/hardware.h>
#include <asm/arch/orion.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
/*
* Enable and issue soft reset
*/
orion_setbits(CPU_RESET_MASK, (1 << 2));
orion_setbits(CPU_SOFT_RESET, 1);
}
#endif
/*
* include/asm-arm/arch-orion/timex.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define ORION_TCLK 166666667
#define CLOCK_TICK_RATE ORION_TCLK
/*
* include/asm-arm/arch-orion/uncompress.h
*
* Tzachi Perelstein <tzachi@marvell.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/orion.h>
#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
#define LSR_THRE 0x20
static void putc(const char c)
{
int j = 0x1000;
while (--j && !(*MV_UART_LSR & LSR_THRE))
barrier();
*MV_UART_THR = c;
}
static void flush(void)
{
}
static void orion_early_putstr(const char *ptr)
{
char c;
while ((c = *ptr++) != '\0') {
if (c == '\n')
putc('\r');
putc(c);
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
/*
* include/asm-arm/arch-orion/vmalloc.h
*/
#define VMALLOC_END 0xf0000000
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