Commit 58ce7341 authored by CQ Tang's avatar CQ Tang Committed by Luis Henriques

iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG

commit fda3bec1 upstream.

This is a 32-bit register. Apparently harmless on real hardware, but
causing justified warnings in simulation.
Signed-off-by: default avatarCQ Tang <cq.tang@intel.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: default avatarLuis Henriques <luis.henriques@canonical.com>
parent 6b90ca7b
...@@ -1246,7 +1246,7 @@ void dmar_disable_qi(struct intel_iommu *iommu) ...@@ -1246,7 +1246,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
raw_spin_lock_irqsave(&iommu->register_lock, flags); raw_spin_lock_irqsave(&iommu->register_lock, flags);
sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_QIES)) if (!(sts & DMA_GSTS_QIES))
goto end; goto end;
......
...@@ -504,7 +504,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu) ...@@ -504,7 +504,7 @@ static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
raw_spin_lock_irqsave(&iommu->register_lock, flags); raw_spin_lock_irqsave(&iommu->register_lock, flags);
sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); sts = readl(iommu->reg + DMAR_GSTS_REG);
if (!(sts & DMA_GSTS_IRES)) if (!(sts & DMA_GSTS_IRES))
goto end; goto end;
......
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