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Commit 59ed6a6e authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: Infrastructure changes to MPC85xx sub-arch from OCP to platform_device 

- Described all devices available on current MPC85xx CPUs (mem & irq)

- Added cpu descriptions for the MPC8540, MPC8541, MPC8541, MPC8555,
  MPC8555E, and MPC8560.

* Removed OCP usage from MPC85xx sub-arch
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 64b200c0
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Showing with 688 additions and 294 deletions
arch/ppc/Kconfig
View file @ 59ed6a6e
......@@ -678,7 +678,7 @@ config 8272
config CPM2
bool
depends on 8260 || MPC8560
depends on 8260 || MPC8560 || MPC8555
default y
help
The CPM2 (Communications Processor Module) is a coprocessor on
......
arch/ppc/platforms/85xx/Kconfig
View file @ 59ed6a6e
......@@ -62,11 +62,6 @@ config 85xx_PCI2
depends on MPC8555_CDS
default y
config FSL_OCP
bool
depends on 85xx
default y
config PPC_GEN550
bool
depends on MPC8540 || SBC8560 || MPC8555
......
arch/ppc/platforms/85xx/Makefile
View file @ 59ed6a6e
#
# Makefile for the PowerPC 85xx linux kernel.
#
obj-$(CONFIG_85xx) += mpc85xx_sys.o mpc85xx_devices.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o
obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o
obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o
obj-$(CONFIG_MPC8540) += mpc8540.o
obj-$(CONFIG_MPC8555) += mpc8555.o
obj-$(CONFIG_MPC8560) += mpc8560.o
arch/ppc/platforms/85xx/mpc8540.c deleted 100644 → 0
View file @ 64b200c0
/*
* arch/ppc/platforms/85xx/mpc8540.c
*
* MPC8540 I/O descriptions
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2004 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <asm/mpc85xx.h>
#include <asm/ocp.h>
/* These should be defined in platform code */
extern struct ocp_gfar_data mpc85xx_tsec1_def;
extern struct ocp_gfar_data mpc85xx_tsec2_def;
extern struct ocp_gfar_data mpc85xx_fec_def;
extern struct ocp_mpc_i2c_data mpc85xx_i2c1_def;
/* We use offsets for paddr since we do not know at compile time
* what CCSRBAR is, platform code should fix this up in
* setup_arch
*
* Only the first IRQ is given even if a device has
* multiple lines associated with ita
*/
struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 0,
.paddr = MPC85xx_IIC1_OFFSET,
.irq = MPC85xx_IRQ_IIC1,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_i2c1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = MPC85xx_UART0_OFFSET,
.irq = MPC85xx_IRQ_DUART,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = MPC85xx_UART1_OFFSET,
.irq = MPC85xx_IRQ_DUART,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 0,
.paddr = MPC85xx_ENET1_OFFSET,
.irq = MPC85xx_IRQ_TSEC1_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 1,
.paddr = MPC85xx_ENET2_OFFSET,
.irq = MPC85xx_IRQ_TSEC2_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec2_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 2,
.paddr = MPC85xx_ENET3_OFFSET,
.irq = MPC85xx_IRQ_FEC,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_fec_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_DMA,
.index = 0,
.paddr = MPC85xx_DMA_OFFSET,
.irq = MPC85xx_IRQ_DMA0,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_PERFMON,
.index = 0,
.paddr = MPC85xx_PERFMON_OFFSET,
.irq = MPC85xx_IRQ_PERFMON,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_INVALID
}
};
arch/ppc/platforms/85xx/mpc8555.c deleted 100644 → 0
View file @ 64b200c0
/*
* arch/ppc/platform/85xx/mpc8555.c
*
* MPC8555 I/O descriptions
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2004 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <asm/mpc85xx.h>
#include <asm/ocp.h>
/* These should be defined in platform code */
extern struct ocp_gfar_data mpc85xx_tsec1_def;
extern struct ocp_gfar_data mpc85xx_tsec2_def;
extern struct ocp_mpc_i2c_data mpc85xx_i2c1_def;
/* We use offsets for paddr since we do not know at compile time
* what CCSRBAR is, platform code should fix this up in
* setup_arch
*
* Only the first IRQ is given even if a device has
* multiple lines associated with ita
*/
struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 0,
.paddr = MPC85xx_IIC1_OFFSET,
.irq = MPC85xx_IRQ_IIC1,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_i2c1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_16550,
.index = 0,
.paddr = MPC85xx_UART0_OFFSET,
.irq = MPC85xx_IRQ_DUART,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_16550,
.index = 1,
.paddr = MPC85xx_UART1_OFFSET,
.irq = MPC85xx_IRQ_DUART,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 0,
.paddr = MPC85xx_ENET1_OFFSET,
.irq = MPC85xx_IRQ_TSEC1_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 1,
.paddr = MPC85xx_ENET2_OFFSET,
.irq = MPC85xx_IRQ_TSEC2_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec2_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_DMA,
.index = 0,
.paddr = MPC85xx_DMA_OFFSET,
.irq = MPC85xx_IRQ_DMA0,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_SEC2,
.index = 0,
.paddr = MPC85xx_SEC2_OFFSET,
.irq = MPC85xx_IRQ_SEC2,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_PERFMON,
.index = 0,
.paddr = MPC85xx_PERFMON_OFFSET,
.irq = MPC85xx_IRQ_PERFMON,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_INVALID
}
};
arch/ppc/platforms/85xx/mpc8560.c deleted 100644 → 0
View file @ 64b200c0
/*
* arch/ppc/platforms/85xx/mpc8560.c
*
* MPC8560 I/O descriptions
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2004 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <asm/mpc85xx.h>
#include <asm/ocp.h>
/* These should be defined in platform code */
extern struct ocp_gfar_data mpc85xx_tsec1_def;
extern struct ocp_gfar_data mpc85xx_tsec2_def;
extern struct ocp_mpc_i2c_data mpc85xx_i2c1_def;
/* We use offsets for paddr since we do not know at compile time
* what CCSRBAR is, platform code should fix this up in
* setup_arch
*
* Only the first IRQ is given even if a device has
* multiple lines associated with ita
*/
struct ocp_def core_ocp[] = {
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 0,
.paddr = MPC85xx_IIC1_OFFSET,
.irq = MPC85xx_IRQ_IIC1,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_i2c1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 0,
.paddr = MPC85xx_ENET1_OFFSET,
.irq = MPC85xx_IRQ_TSEC1_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec1_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_GFAR,
.index = 1,
.paddr = MPC85xx_ENET2_OFFSET,
.irq = MPC85xx_IRQ_TSEC2_TX,
.pm = OCP_CPM_NA,
.additions = &mpc85xx_tsec2_def,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_DMA,
.index = 0,
.paddr = MPC85xx_DMA_OFFSET,
.irq = MPC85xx_IRQ_DMA0,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_PERFMON,
.index = 0,
.paddr = MPC85xx_PERFMON_OFFSET,
.irq = MPC85xx_IRQ_PERFMON,
.pm = OCP_CPM_NA,
},
{ .vendor = OCP_VENDOR_INVALID
}
};
arch/ppc/platforms/85xx/mpc85xx_devices.c 0 → 100644
View file @ 59ed6a6e
This diff is collapsed.
arch/ppc/platforms/85xx/mpc85xx_sys.c 0 → 100644
View file @ 59ed6a6e
/*
* arch/ppc/platforms/85xx/mpc85xx_sys.c
*
* MPC85xx System descriptions
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2005 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <asm/ppc_sys.h>
struct ppc_sys_spec *cur_ppc_sys_spec;
struct ppc_sys_spec ppc_sys_specs[] = {
{
.ppc_sys_name = "MPC8540",
.mask = 0xFFFF0000,
.value = 0x80300000,
.num_devices = 9,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_FEC, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON,
},
},
{
.ppc_sys_name = "MPC8560",
.mask = 0xFFFF0000,
.value = 0x80700000,
.num_devices = 19,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3, MPC85xx_CPM_SCC4,
MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
MPC85xx_CPM_MCC1, MPC85xx_CPM_MCC2,
},
},
{
.ppc_sys_name = "MPC8541",
.mask = 0xFFFF0000,
.value = 0x80720000,
.num_devices = 12,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
},
},
{
.ppc_sys_name = "MPC8541E",
.mask = 0xFFFF0000,
.value = 0x807A0000,
.num_devices = 13,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON, MPC85xx_SEC2,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C,
MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2,
},
},
{
.ppc_sys_name = "MPC8555",
.mask = 0xFFFF0000,
.value = 0x80710000,
.num_devices = 19,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
MPC85xx_CPM_USB,
},
},
{
.ppc_sys_name = "MPC8555E",
.mask = 0xFFFF0000,
.value = 0x80790000,
.num_devices = 20,
.device_list = (enum ppc_sys_devices[])
{
MPC85xx_TSEC1, MPC85xx_TSEC2, MPC85xx_IIC1,
MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
MPC85xx_PERFMON, MPC85xx_SEC2,
MPC85xx_CPM_SPI, MPC85xx_CPM_I2C, MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2, MPC85xx_CPM_SCC3,
MPC85xx_CPM_FCC1, MPC85xx_CPM_FCC2, MPC85xx_CPM_FCC3,
MPC85xx_CPM_SMC1, MPC85xx_CPM_SMC2,
MPC85xx_CPM_USB,
},
},
{ /* default match */
.ppc_sys_name = "",
.mask = 0x00000000,
.value = 0x00000000,
},
};
arch/ppc/syslib/ppc85xx_common.c
View file @ 59ed6a6e
......@@ -20,7 +20,6 @@
#include <asm/mpc85xx.h>
#include <asm/mmu.h>
#include <asm/ocp.h>
/* ************************************************************************ */
/* Return the value of CCSRBAR for the current board */
......@@ -31,16 +30,4 @@ get_ccsrbar(void)
return BOARD_CCSRBAR;
}
/* ************************************************************************ */
/* Update the 85xx OCP tables paddr field */
void
mpc85xx_update_paddr_ocp(struct ocp_device *dev, void *arg)
{
phys_addr_t ccsrbar;
if (arg) {
ccsrbar = *(phys_addr_t *)arg;
dev->def->paddr += ccsrbar;
}
}
EXPORT_SYMBOL(get_ccsrbar);
arch/ppc/syslib/ppc85xx_common.h
View file @ 59ed6a6e
......@@ -18,12 +18,8 @@
#include <linux/config.h>
#include <linux/init.h>
#include <asm/ocp.h>
/* Provide access to ccsrbar for any modules, etc */
phys_addr_t get_ccsrbar(void);
/* Update the 85xx OCP tables paddr field */
void mpc85xx_update_paddr_ocp(struct ocp_device *dev, void *ccsrbar);
#endif /* __PPC_SYSLIB_PPC85XX_COMMON_H */
arch/ppc/syslib/ppc85xx_setup.c
View file @ 59ed6a6e
......@@ -27,7 +27,6 @@
#include <asm/mpc85xx.h>
#include <asm/immap_85xx.h>
#include <asm/mmu.h>
#include <asm/ocp.h>
#include <asm/kgdb.h>
#include <syslib/ppc85xx_setup.h>
......
include/asm-ppc/irq.h
View file @ 59ed6a6e
......@@ -199,6 +199,7 @@ static __inline__ int irq_canonicalize(int irq)
#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
......
include/asm-ppc/mpc85xx.h
View file @ 59ed6a6e
......@@ -103,6 +103,14 @@ extern unsigned char __res[];
#define MPC85xx_CPM_SIZE (0x40000)
#define MPC85xx_DMA_OFFSET (0x21000)
#define MPC85xx_DMA_SIZE (0x01000)
#define MPC85xx_DMA0_OFFSET (0x21100)
#define MPC85xx_DMA0_SIZE (0x00080)
#define MPC85xx_DMA1_OFFSET (0x21180)
#define MPC85xx_DMA1_SIZE (0x00080)
#define MPC85xx_DMA2_OFFSET (0x21200)
#define MPC85xx_DMA2_SIZE (0x00080)
#define MPC85xx_DMA3_OFFSET (0x21280)
#define MPC85xx_DMA3_SIZE (0x00080)
#define MPC85xx_ENET1_OFFSET (0x24000)
#define MPC85xx_ENET1_SIZE (0x01000)
#define MPC85xx_ENET2_OFFSET (0x25000)
......@@ -139,6 +147,34 @@ extern phys_addr_t get_ccsrbar(void);
#define CCSRBAR BOARD_CCSRBAR
#endif
enum ppc_sys_devices {
MPC85xx_TSEC1,
MPC85xx_TSEC2,
MPC85xx_FEC,
MPC85xx_IIC1,
MPC85xx_DMA0,
MPC85xx_DMA1,
MPC85xx_DMA2,
MPC85xx_DMA3,
MPC85xx_DUART,
MPC85xx_PERFMON,
MPC85xx_SEC2,
MPC85xx_CPM_SPI,
MPC85xx_CPM_I2C,
MPC85xx_CPM_USB,
MPC85xx_CPM_SCC1,
MPC85xx_CPM_SCC2,
MPC85xx_CPM_SCC3,
MPC85xx_CPM_SCC4,
MPC85xx_CPM_FCC1,
MPC85xx_CPM_FCC2,
MPC85xx_CPM_FCC3,
MPC85xx_CPM_MCC1,
MPC85xx_CPM_MCC2,
MPC85xx_CPM_SMC1,
MPC85xx_CPM_SMC2,
};
#endif /* CONFIG_85xx */
#endif /* __ASM_MPC85xx_H__ */
#endif /* __KERNEL__ */
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