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Commit 5aceaab3 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'tegra-for-3.14-dt' of... 

Merge tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

From Stephen Warren:
ARM: tegra: device tree changes

This branch contains all the changes to Tegra's device tree. The
highlights are:

* Many patches for Tegra124 SoC support, and the Venice2 board which
  uses that SoC.
* Conversion to use more headers providing named constants for pinctrl
  and key codes, which improves readability.
* A few cleanups.

This branch is based on tag tegra-for-3.14-dmas-resets-rework in order
to avoid conflicts with the DT changes required to use the common
bindings for DMAs and resets.

* tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits)
  ARM: tegra: Add SPI controller nodes for Tegra124
  ARM: tegra: Fix misconfiguration of pin PH2 on Venice2
  ARM: tegra: fix pinctrl misconfiguration on Venice2
  ARM: tegra: add default pinctrl nodes for Venice2
  ARM: tegra: correct Colibri T20 regulator settings
  ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
  ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines
  ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines
  ARM: tegra: Add header file for pinctrl constants
  ARM: tegra: convert device tree files to use key defines
  ARM: tegra: Enable PWM on Venice2
  ARM: tegra: Add Tegra124 PWM support
  ARM: tegra: add sound card to Venice2 DT
  ARM: tegra: add audio-related device to Tegra124 DT
  ARM: tegra: enable I2C controllers on Venice2
  ARM: tegra: add I2C controllers to Tegra124 DT
  ARM: tegra: add MMC controllers to Tegra124 DT
  ARM: tegra: add Tegra124 pinmux node to DT
  ARM: tegra: add APB DMA controller to Tegra124 DT
  ARM: tegra: add reset properties to Tegra124 DTs
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 770039fe 9f1ac560
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Showing with 1922 additions and 1015 deletions
arch/arm/boot/dts/tegra114-dalmore.dts
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arch/arm/boot/dts/tegra114.dtsi
View file @ 5aceaab3
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
......@@ -15,7 +16,7 @@ aliases {
serial3 = &uartd;
};
gic: interrupt-controller {
gic: interrupt-controller@50041000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
......@@ -39,14 +40,14 @@ timer@60005000 {
clocks = <&tegra_car TEGRA114_CLK_TIMER>;
};
tegra_car: clock {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra114-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
apbdma: dma {
apbdma: dma@6000a000 {
compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -87,12 +88,12 @@ apbdma: dma {
#dma-cells = <1>;
};
ahb: ahb {
ahb: ahb@6000c004 {
compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
reg = <0x6000c004 0x14c>;
};
gpio: gpio {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
......@@ -109,7 +110,7 @@ gpio: gpio {
interrupt-controller;
};
pinmux: pinmux {
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra114-pinmux";
reg = <0x70000868 0x148 /* Pad control registers */
0x70003000 0x40c>; /* Mux registers */
......@@ -175,7 +176,7 @@ uartd: serial@70006300 {
status = "disabled";
};
pwm: pwm {
pwm: pwm@7000a000 {
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
......@@ -350,14 +351,14 @@ spi@7000de00 {
status = "disabled";
};
rtc {
rtc@7000e000 {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_RTC>;
};
kbc {
kbc@7000e200 {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
......@@ -367,14 +368,14 @@ kbc {
status = "disabled";
};
pmc {
pmc@7000e400 {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
iommu {
iommu@70019010 {
compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
reg = <0x70019010 0x02c
0x700191f0 0x010
......@@ -385,7 +386,7 @@ iommu {
nvidia,ahb = <&ahb>;
};
ahub {
ahub@70080000 {
compatible = "nvidia,tegra114-ahub";
reg = <0x70080000 0x200>,
<0x70080200 0x100>,
......
arch/arm/boot/dts/tegra124-venice2.dts
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arch/arm/boot/dts/tegra124.dtsi
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arch/arm/boot/dts/tegra20-colibri-512.dtsi
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arch/arm/boot/dts/tegra20-harmony.dts
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arch/arm/boot/dts/tegra20-iris-512.dts
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......@@ -6,61 +6,61 @@ / {
model = "Toradex Colibri T20 512MB on Iris";
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
};
};
pinmux {
pinmux@70000014 {
state_default: pinmux {
hdint {
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
i2cddc {
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdio4 {
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
uarta {
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
uartd {
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
};
usb@c5000000 {
serial@70006000 {
status = "okay";
};
usb-phy@c5000000 {
serial@70006300 {
status = "okay";
};
usb@c5008000 {
i2c_ddc: i2c@7000c400 {
status = "okay";
};
usb-phy@c5008000 {
usb@c5000000 {
status = "okay";
};
serial@70006000 {
usb-phy@c5000000 {
status = "okay";
};
serial@70006300 {
usb@c5008000 {
status = "okay";
};
i2c_ddc: i2c@7000c400 {
usb-phy@c5008000 {
status = "okay";
};
......
arch/arm/boot/dts/tegra20-medcom-wide.dts
View file @ 5aceaab3
......@@ -6,7 +6,7 @@ / {
model = "Avionic Design Medcom-Wide board";
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
pwm {
pwm@7000a000 {
status = "okay";
};
......
arch/arm/boot/dts/tegra20-paz00.dts
View file @ 5aceaab3
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
......@@ -10,8 +11,8 @@ memory {
reg = <0x00000000 0x20000000>;
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
......@@ -23,7 +24,7 @@ hdmi {
};
};
pinmux {
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -177,39 +178,39 @@ conf_ata {
"gpu", "gpu7", "gpv", "i2cp", "pta",
"rm", "sdio1", "slxk", "spdo", "uac",
"uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_crtp {
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
"dtc", "dte", "slxa", "slxc", "slxd",
"spdi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_csus {
nvidia,pins = "csus", "spia", "spib", "spid",
"spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ddc {
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
"spic", "spig", "uaa", "uab";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_dta {
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
"spie", "spih", "uad", "uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_hdint {
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
......@@ -218,23 +219,23 @@ conf_hdint {
"ld13", "ld14", "ld15", "ld16", "ld17",
"ldc", "ldi", "lhs", "lsc0", "lspi",
"lvs", "pmc";
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
conf_lcsn {
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
"lm0", "lm1", "lpp", "lpw0", "lpw1",
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "lvp1", "sdb";
nvidia,tristate = <1>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
};
};
......@@ -268,7 +269,7 @@ hdmi_ddc: i2c@7000c400 {
clock-frequency = <100000>;
};
nvec {
nvec@7000c500 {
compatible = "nvidia,nvec";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
......@@ -417,7 +418,7 @@ adt7461@4c {
};
};
pmc {
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
......@@ -474,7 +475,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......@@ -488,7 +489,7 @@ gpio-keys {
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
};
......
arch/arm/boot/dts/tegra20-plutux.dts
View file @ 5aceaab3
......@@ -6,8 +6,8 @@ / {
model = "Avionic Design Plutux board";
compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
};
};
......
arch/arm/boot/dts/tegra20-seaboard.dts
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arch/arm/boot/dts/tegra20-tamonten.dtsi
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......@@ -8,8 +8,8 @@ memory {
reg = <0x00000000 0x20000000>;
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
vdd-supply = <&hdmi_vdd_reg>;
pll-supply = <&hdmi_pll_reg>;
......@@ -19,7 +19,7 @@ hdmi {
};
};
pinmux {
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -176,50 +176,50 @@ conf_ata {
"gmb", "gmc", "gmd", "gme", "gpu7",
"gpv", "i2cp", "pta", "rm", "slxa",
"slxk", "spia", "spib", "uac";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_csus {
nvidia,pins = "csus", "spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_crtp {
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
"dtc", "dte", "dtf", "gpu", "sdio1",
"slxc", "slxd", "spdi", "spdo", "spig",
"uda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ddc {
nvidia,pins = "ddc", "dta", "dtd", "kbca",
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
"sdc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "owc", "sdb";
nvidia,tristate = <1>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_irrx {
nvidia,pins = "irrx", "irtx", "sdd", "spic",
"spie", "spih", "uaa", "uab", "uad",
"uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
......@@ -229,12 +229,12 @@ conf_ld0 {
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
"lvs", "pmc";
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
};
......@@ -457,7 +457,7 @@ temperature-sensor@4c {
};
};
pmc {
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <5000>;
......@@ -467,7 +467,7 @@ pmc {
nvidia,sys-clock-req-active-high;
};
pcie-controller {
pcie-controller@80003000 {
pex-clk-supply = <&pci_clk_reg>;
vdd-supply = <&pci_vdd_reg>;
};
......@@ -492,7 +492,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......
arch/arm/boot/dts/tegra20-tec.dts
View file @ 5aceaab3
......@@ -6,8 +6,8 @@ / {
model = "Avionic Design Tamonten Evaluation Carrier";
compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
};
};
......@@ -32,7 +32,7 @@ wm8903: wm8903@1a {
};
};
pcie-controller {
pcie-controller@80003000 {
status = "okay";
pci@1,0 {
......
arch/arm/boot/dts/tegra20-trimslice.dts
View file @ 5aceaab3
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
......@@ -10,8 +11,8 @@ memory {
reg = <0x00000000 0x40000000>;
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
......@@ -23,7 +24,7 @@ hdmi {
};
};
pinmux {
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -191,49 +192,49 @@ conf_ata {
"dtb", "dtc", "dtd", "dte", "gmb",
"gme", "i2cp", "pta", "slxc", "slxd",
"spdi", "spdo", "uda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_atb {
nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
"gma", "gmc", "gmd", "gpu", "gpu7",
"gpv", "sdio1", "slxa", "slxk", "uac";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_csus {
nvidia,pins = "csus", "spia", "spib",
"spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ddc {
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "pmc";
nvidia,tristate = <1>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_irrx {
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
"kbcc", "kbcd", "kbce", "kbcf", "owc",
"spic", "spie", "spig", "spih", "uaa",
"uab", "uad", "uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
......@@ -243,17 +244,17 @@ conf_ld0 {
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
"lvs", "sdb";
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
conf_spif {
nvidia,pins = "spif";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
};
......@@ -301,7 +302,7 @@ rtc@56 {
};
};
pmc {
pmc@7000e400 {
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
......@@ -310,7 +311,7 @@ pmc {
nvidia,sys-clock-req-active-high;
};
pcie-controller {
pcie-controller@80003000 {
status = "okay";
pex-clk-supply = <&pci_clk_reg>;
vdd-supply = <&pci_vdd_reg>;
......@@ -366,7 +367,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......@@ -380,7 +381,7 @@ gpio-keys {
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
};
......
arch/arm/boot/dts/tegra20-ventana.dts
View file @ 5aceaab3
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
......@@ -10,8 +11,8 @@ memory {
reg = <0x00000000 0x40000000>;
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
......@@ -23,7 +24,7 @@ hdmi {
};
};
pinmux {
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -189,50 +190,50 @@ conf_ata {
"irtx", "pta", "rm", "sdc", "sdd",
"slxc", "slxd", "slxk", "spdi", "spdo",
"uac", "uad", "uca", "ucb", "uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ate {
nvidia,pins = "ate", "csus", "dap3", "gmd",
"gpv", "owc", "spia", "spib", "spic",
"spid", "spie", "spig";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_crtp {
nvidia,pins = "crtp", "gmb", "slxa", "spih";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_dte {
nvidia,pins = "dte", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
nvidia,tristate = <1>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf", "sdio1", "uaa", "uab";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
......@@ -242,22 +243,22 @@ conf_ld0 {
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
"lvp1", "lvs", "pmc", "sdb";
nvidia,tristate = <0>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <1>;
nvidia,low-power-mode = <3>;
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <31>;
nvidia,pull-up-strength = <31>;
nvidia,slew-rate-rising = <3>;
nvidia,slew-rate-falling = <3>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
};
};
......@@ -492,7 +493,7 @@ temperature-sensor@4c {
};
};
pmc {
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
......@@ -556,7 +557,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......@@ -570,7 +571,7 @@ gpio-keys {
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <116>; /* KEY_POWER */
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
};
......
arch/arm/boot/dts/tegra20-whistler.dts
View file @ 5aceaab3
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
......@@ -10,8 +11,8 @@ memory {
reg = <0x00000000 0x20000000>;
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
......@@ -23,7 +24,7 @@ hdmi {
};
};
pinmux {
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -189,8 +190,8 @@ conf_ata {
"kbcf", "sdc", "sdd", "spie", "spig",
"spih", "uaa", "uab", "uad", "uca",
"ucb";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_atd {
nvidia,pins = "atd", "ate", "cdev1", "csus",
......@@ -198,54 +199,54 @@ conf_atd {
"dtf", "gpu", "gpu7", "gpv", "i2cp",
"rm", "sdio1", "slxa", "slxc", "slxd",
"slxk", "spdi", "spdo", "uac", "uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_cdev2 {
nvidia,pins = "cdev2", "spia", "spib";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "lc", "pmca",
"pmcb", "pmcc", "pmcd", "xm2c",
"xm2d";
nvidia,pull = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_crtp {
nvidia,pins = "crtp";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd",
"spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_gme {
nvidia,pins = "gme", "owc", "pta", "spic";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
conf_ls {
nvidia,pins = "ls", "pmce";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
drive_dap1 {
nvidia,pins = "drive_dap1";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <1>;
nvidia,low-power-mode = <0>;
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
nvidia,pull-down-strength = <0>;
nvidia,pull-up-strength = <0>;
nvidia,slew-rate-rising = <0>;
nvidia,slew-rate-falling = <0>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
};
};
};
......@@ -495,7 +496,20 @@ vrtc {
};
};
pmc {
kbc@7000e200 {
status = "okay";
nvidia,debounce-delay-ms = <20>;
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2>;
nvidia,kbc-col-pins = <16 17>;
nvidia,wakeup-source;
linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
MATRIX_KEY(0x01, 0x00, KEY_HOME)
MATRIX_KEY(0x01, 0x01, KEY_BACK)
MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
......@@ -543,7 +557,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......@@ -551,25 +565,12 @@ clk32k_in: clock {
};
};
kbc {
status = "okay";
nvidia,debounce-delay-ms = <20>;
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2>;
nvidia,kbc-col-pins = <16 17>;
nvidia,wakeup-source;
linux,keymap = <0x00000074 /* KEY_POWER */
0x01000066 /* KEY_HOME */
0x0101009E /* KEY_BACK */
0x0201008B>; /* KEY_MENU */
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb0_vbus_reg: regulator {
usb0_vbus_reg: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb0_vbus";
......
arch/arm/boot/dts/tegra20.dtsi
View file @ 5aceaab3
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
......@@ -16,7 +17,7 @@ aliases {
serial4 = &uarte;
};
host1x {
host1x@50000000 {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
......@@ -30,7 +31,7 @@ host1x {
ranges = <0x54000000 0x54000000 0x04000000>;
mpe {
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
......@@ -39,7 +40,7 @@ mpe {
reset-names = "mpe";
};
vi {
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
......@@ -48,7 +49,7 @@ vi {
reset-names = "vi";
};
epp {
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
......@@ -57,7 +58,7 @@ epp {
reset-names = "epp";
};
isp {
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
......@@ -66,7 +67,7 @@ isp {
reset-names = "isp";
};
gr2d {
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
......@@ -75,9 +76,9 @@ gr2d {
reset-names = "2d";
};
gr3d {
gr3d@54140000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
reg = <0x54140000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
......@@ -113,7 +114,7 @@ rgb {
};
};
hdmi {
hdmi@54280000 {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
......@@ -125,7 +126,7 @@ hdmi {
status = "disabled";
};
tvo {
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
......@@ -133,9 +134,9 @@ tvo {
status = "disabled";
};
dsi {
dsi@542c0000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
reg = <0x542c0000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>;
resets = <&tegra_car 48>;
reset-names = "dsi";
......@@ -151,7 +152,7 @@ timer@50004600 {
clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
intc: interrupt-controller {
intc: interrupt-controller@50041000 {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
0x50040100 0x0100>;
......@@ -159,7 +160,7 @@ intc: interrupt-controller {
#interrupt-cells = <3>;
};
cache-controller {
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
......@@ -178,14 +179,14 @@ timer@60005000 {
clocks = <&tegra_car TEGRA20_CLK_TIMER>;
};
tegra_car: clock {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
apbdma: dma {
apbdma: dma@6000a000 {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -210,12 +211,12 @@ apbdma: dma {
#dma-cells = <1>;
};
ahb {
ahb@6000c004 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
......@@ -231,7 +232,7 @@ gpio: gpio {
interrupt-controller;
};
pinmux: pinmux {
pinmux: pinmux@70000014 {
compatible = "nvidia,tegra20-pinmux";
reg = <0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
......@@ -239,12 +240,12 @@ pinmux: pinmux {
0x70000868 0xa8>; /* Pad control registers */
};
das {
das@70000c00 {
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
tegra_ac97: ac97 {
tegra_ac97: ac97@70002000 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
......@@ -352,7 +353,7 @@ uarte: serial@70006400 {
status = "disabled";
};
pwm: pwm {
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
......@@ -362,7 +363,7 @@ pwm: pwm {
status = "disabled";
};
rtc {
rtc@7000e000 {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -503,7 +504,7 @@ spi@7000da00 {
status = "disabled";
};
kbc {
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
......@@ -513,7 +514,7 @@ kbc {
status = "disabled";
};
pmc {
pmc@7000e400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
......@@ -527,7 +528,7 @@ memory-controller@7000f000 {
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
iommu@7000f024 {
compatible = "nvidia,tegra20-gart";
reg = <0x7000f024 0x00000018 /* controller registers */
0x58000000 0x02000000>; /* GART aperture */
......@@ -540,7 +541,7 @@ memory-controller@7000f400 {
#size-cells = <0>;
};
pcie-controller {
pcie-controller@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
......
arch/arm/boot/dts/tegra30-beaver.dts
View file @ 5aceaab3
......@@ -10,7 +10,7 @@ memory {
reg = <0x80000000 0x7ff00000>;
};
pcie-controller {
pcie-controller@00003000 {
status = "okay";
pex-clk-supply = <&sys_3v3_pexs_reg>;
vdd-supply = <&ldo1_reg>;
......@@ -31,8 +31,8 @@ pci@3,0 {
};
};
host1x {
hdmi {
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&sys_3v3_reg>;
......@@ -44,7 +44,7 @@ hdmi {
};
};
pinmux {
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -52,8 +52,8 @@ state_default: pinmux {
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
......@@ -62,14 +62,14 @@ sdmmc1_cmd_pz1 {
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
......@@ -78,15 +78,15 @@ sdmmc3_cmd_pa7 {
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4";
nvidia,function = "sdmmc3";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
......@@ -98,8 +98,8 @@ sdmmc4_dat0_paa0 {
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
dap2_fs_pa2 {
nvidia,pins = "dap2_fs_pa2",
......@@ -107,18 +107,18 @@ dap2_fs_pa2 {
"dap2_din_pa4",
"dap2_dout_pa5";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
pex_l1_prsnt_n_pdd4 {
nvidia,pins = "pex_l1_prsnt_n_pdd4",
"pex_l1_clkreq_n_pdd6";
nvidia,pull = <2>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <0>;
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,pull-down-strength = <46>;
nvidia,pull-up-strength = <42>;
nvidia,slew-rate-rising = <1>;
......@@ -159,7 +159,7 @@ i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
rt5640: rt5640 {
rt5640: rt5640@1c {
compatible = "realtek,rt5640";
reg = <0x1c>;
interrupt-parent = <&gpio>;
......@@ -168,19 +168,6 @@ rt5640: rt5640 {
<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
};
tps62361 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
};
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
......@@ -284,6 +271,19 @@ ldo8_reg: ldo8 {
};
};
};
tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
};
};
spi@7000da00 {
......@@ -296,13 +296,7 @@ spi-flash@1 {
};
};
ahub {
i2s@70080400 {
status = "okay";
};
};
pmc {
pmc@7000e400 {
status = "okay";
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
......@@ -314,6 +308,12 @@ pmc {
nvidia,sys-clock-req-active-high;
};
ahub@70080000 {
i2s@70080400 {
status = "okay";
};
};
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
......@@ -342,7 +342,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......@@ -350,6 +350,19 @@ clk32k_in: clock {
};
};
gpio-leds {
compatible = "gpio-leds";
gpled1 {
label = "LED1"; /* CR5A1 (blue) */
gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
};
gpled2 {
label = "LED2"; /* CR4A2 (green) */
gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -453,19 +466,6 @@ sys_3v3_pexs_reg: regulator@7 {
};
};
gpio-leds {
compatible = "gpio-leds";
gpled1 {
label = "LED1"; /* CR5A1 (blue) */
gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
};
gpled2 {
label = "LED2"; /* CR4A2 (green) */
gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "nvidia,tegra-audio-rt5640-beaver",
"nvidia,tegra-audio-rt5640";
......
arch/arm/boot/dts/tegra30-cardhu-a02.dts
View file @ 5aceaab3
......@@ -8,6 +8,13 @@ / {
model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -83,12 +90,5 @@ vdd_bl_reg: regulator@105 {
gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
};
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View file @ 5aceaab3
......@@ -8,6 +8,13 @@ / {
model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -95,11 +102,4 @@ vdd_bl2_reg: regulator@106 {
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
};
};
sdhci@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
};
arch/arm/boot/dts/tegra30-cardhu.dtsi
View file @ 5aceaab3
......@@ -31,7 +31,7 @@ memory {
reg = <0x80000000 0x40000000>;
};
pcie-controller {
pcie-controller@00003000 {
status = "okay";
pex-clk-supply = <&pex_hvdd_3v3_reg>;
vdd-supply = <&ldo1_reg>;
......@@ -51,7 +51,7 @@ pci@3,0 {
};
};
pinmux {
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -59,8 +59,8 @@ state_default: pinmux {
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
......@@ -69,14 +69,14 @@ sdmmc1_cmd_pz1 {
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
......@@ -85,15 +85,15 @@ sdmmc3_cmd_pa7 {
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4";
nvidia,function = "sdmmc3";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
......@@ -105,8 +105,8 @@ sdmmc4_dat0_paa0 {
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
dap2_fs_pa2 {
nvidia,pins = "dap2_fs_pa2",
......@@ -114,17 +114,17 @@ dap2_fs_pa2 {
"dap2_din_pa4",
"dap2_dout_pa5";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <0>;
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,pull-down-strength = <46>;
nvidia,pull-up-strength = <42>;
nvidia,slew-rate-rising = <1>;
nvidia,slew-rate-falling = <1>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
};
uart3_txd_pw6 {
nvidia,pins = "uart3_txd_pw6",
......@@ -132,8 +132,8 @@ uart3_txd_pw6 {
"uart3_rts_n_pc0",
"uart3_rxd_pw7";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
};
......@@ -302,7 +302,7 @@ temperature-sensor@4c {
interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
};
tps62361 {
tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
......@@ -326,13 +326,7 @@ spi-flash@1 {
};
};
ahub {
i2s@70080400 {
status = "okay";
};
};
pmc {
pmc@7000e400 {
status = "okay";
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
......@@ -344,6 +338,12 @@ pmc {
nvidia,sys-clock-req-active-high;
};
ahub@70080000 {
i2s@70080400 {
status = "okay";
};
};
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
......@@ -372,7 +372,7 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
......
arch/arm/boot/dts/tegra30.dtsi
View file @ 5aceaab3
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
......@@ -16,7 +17,7 @@ aliases {
serial4 = &uarte;
};
pcie-controller {
pcie-controller@00003000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
......@@ -89,7 +90,7 @@ pci@3,0 {
};
};
host1x {
host1x@50000000 {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
......@@ -103,7 +104,7 @@ host1x {
ranges = <0x54000000 0x54000000 0x04000000>;
mpe {
mpe@54040000 {
compatible = "nvidia,tegra30-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
......@@ -112,7 +113,7 @@ mpe {
reset-names = "mpe";
};
vi {
vi@54080000 {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
......@@ -121,7 +122,7 @@ vi {
reset-names = "vi";
};
epp {
epp@540c0000 {
compatible = "nvidia,tegra30-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
......@@ -130,7 +131,7 @@ epp {
reset-names = "epp";
};
isp {
isp@54100000 {
compatible = "nvidia,tegra30-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
......@@ -139,7 +140,7 @@ isp {
reset-names = "isp";
};
gr2d {
gr2d@54140000 {
compatible = "nvidia,tegra30-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
......@@ -148,7 +149,7 @@ gr2d {
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
};
gr3d {
gr3d@54180000 {
compatible = "nvidia,tegra30-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA30_CLK_GR3D
......@@ -189,7 +190,7 @@ rgb {
};
};
hdmi {
hdmi@54280000 {
compatible = "nvidia,tegra30-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
......@@ -201,7 +202,7 @@ hdmi {
status = "disabled";
};
tvo {
tvo@542c0000 {
compatible = "nvidia,tegra30-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
......@@ -209,7 +210,7 @@ tvo {
status = "disabled";
};
dsi {
dsi@54300000 {
compatible = "nvidia,tegra30-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA30_CLK_DSIA>;
......@@ -227,7 +228,7 @@ timer@50004600 {
clocks = <&tegra_car TEGRA30_CLK_TWD>;
};
intc: interrupt-controller {
intc: interrupt-controller@50041000 {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
0x50040100 0x0100>;
......@@ -235,7 +236,7 @@ intc: interrupt-controller {
#interrupt-cells = <3>;
};
cache-controller {
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
......@@ -256,14 +257,14 @@ timer@60005000 {
clocks = <&tegra_car TEGRA30_CLK_TIMER>;
};
tegra_car: clock {
tegra_car: clock@60006000 {
compatible = "nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
apbdma: dma {
apbdma: dma@6000a000 {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
......@@ -304,12 +305,12 @@ apbdma: dma {
#dma-cells = <1>;
};
ahb: ahb {
ahb: ahb@6000c004 {
compatible = "nvidia,tegra30-ahb";
reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
......@@ -326,7 +327,7 @@ gpio: gpio {
interrupt-controller;
};
pinmux: pinmux {
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra30-pinmux";
reg = <0x70000868 0xd4 /* Pad control registers */
0x70003000 0x3e4>; /* Mux registers */
......@@ -405,7 +406,7 @@ uarte: serial@70006400 {
status = "disabled";
};
pwm: pwm {
pwm: pwm@7000a000 {
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
......@@ -415,7 +416,7 @@ pwm: pwm {
status = "disabled";
};
rtc {
rtc@7000e000 {
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
......@@ -586,7 +587,7 @@ spi@7000de00 {
status = "disabled";
};
kbc {
kbc@7000e200 {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
......@@ -596,14 +597,14 @@ kbc {
status = "disabled";
};
pmc {
pmc@7000e400 {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
memory-controller {
memory-controller@7000f000 {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x010
0x7000f03c 0x1b4
......@@ -612,7 +613,7 @@ memory-controller {
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu {
iommu@7000f010 {
compatible = "nvidia,tegra30-smmu";
reg = <0x7000f010 0x02c
0x7000f1f0 0x010
......@@ -622,7 +623,7 @@ iommu {
nvidia,ahb = <&ahb>;
};
ahub {
ahub@70080000 {
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
0x70080200 0x100>;
......
include/dt-bindings/gpio/tegra-gpio.h
View file @ 5aceaab3
......@@ -43,6 +43,7 @@
#define TEGRA_GPIO_BANK_ID_CC 28
#define TEGRA_GPIO_BANK_ID_DD 29
#define TEGRA_GPIO_BANK_ID_EE 30
#define TEGRA_GPIO_BANK_ID_FF 31
#define TEGRA_GPIO(bank, offset) \
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
......
include/dt-bindings/pinctrl/pinctrl-tegra.h 0 → 100644
View file @ 5aceaab3
/*
* This header provides constants for Tegra pinctrl bindings.
*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
#define _DT_BINDINGS_PINCTRL_TEGRA_H
/*
* Enable/disable for diffeent dt properties. This is applicable for
* properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
* nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
*/
#define TEGRA_PIN_DISABLE 0
#define TEGRA_PIN_ENABLE 1
#define TEGRA_PIN_PULL_NONE 0
#define TEGRA_PIN_PULL_DOWN 1
#define TEGRA_PIN_PULL_UP 2
/* Low power mode driver */
#define TEGRA_PIN_LP_DRIVE_DIV_8 0
#define TEGRA_PIN_LP_DRIVE_DIV_4 1
#define TEGRA_PIN_LP_DRIVE_DIV_2 2
#define TEGRA_PIN_LP_DRIVE_DIV_1 3
/* Rising/Falling slew rate */
#define TEGRA_PIN_SLEW_RATE_FASTEST 0
#define TEGRA_PIN_SLEW_RATE_FAST 1
#define TEGRA_PIN_SLEW_RATE_SLOW 2
#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
#endif
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