msm: smd: initial support for smd v2

- support both v2 and v1 style smd channels
- support both v2 and v1 smsm shared state
- update smsm state defines and smem item enum
- prep work for dealing with smd to qdsp6
- simplify some smem access to minimize use of smem_alloc() at runtime
Signed-off-by: Brian Swetland <swetland@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>

arch/arm/mach-msm/smd_private.h

@@ -43,6 +43,7 @@ struct smem_proc_comm
 #define PC_APPS  0
 #define PC_MODEM 1
 
+#define VERSION_SMD       0
 #define VERSION_QDSP6     4
 #define VERSION_APPS_SBL  6
 #define VERSION_MODEM_SBL 7
@@ -54,14 +55,17 @@ struct smem_shared
 	struct smem_proc_comm proc_comm[4];
 	unsigned version[32];
 	struct smem_heap_info heap_info;
-	struct smem_heap_entry heap_toc[128];
+	struct smem_heap_entry heap_toc[512];
 };
 
-struct smsm_shared
-{
-	unsigned host;
-	unsigned state;
-};
+#define SMSM_V1_SIZE		(sizeof(unsigned) * 8)
+#define SMSM_V1_STATE_APPS	0x0000
+#define SMSM_V1_STATE_MODEM	0x0004
+#define SMSM_V1_STATE_DSP	0x0008
+
+#define SMSM_V2_SIZE		(sizeof(unsigned) * 4)
+#define SMSM_V2_STATE_APPS	0x0004
+#define SMSM_V2_STATE_MODEM	0x000C
 
 struct smsm_interrupt_info
 {
@@ -76,21 +80,31 @@ struct smsm_interrupt_info
 #define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
 #define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
 
-#define SMSM_INIT          0x000001
-#define SMSM_SMDINIT       0x000008
-#define SMSM_RPCINIT       0x000020
-#define SMSM_RESET         0x000040
-#define SMSM_RSA               0x0080
-#define SMSM_RUN           0x000100
-#define SMSM_PWRC              0x0200
-#define SMSM_TIMEWAIT          0x0400
-#define SMSM_TIMEINIT          0x0800
-#define SMSM_PWRC_EARLY_EXIT   0x1000
-#define SMSM_WFPI              0x2000
-#define SMSM_SLEEP             0x4000
-#define SMSM_SLEEPEXIT         0x8000
-#define SMSM_OEMSBL_RELEASE    0x10000
-#define SMSM_PWRC_SUSPEND      0x200000
+#define SMSM_INIT		0x00000001
+#define SMSM_SMDINIT		0x00000008
+#define SMSM_RPCINIT		0x00000020
+#define SMSM_RESET		0x00000040
+#define SMSM_RSA		0x00000080
+#define SMSM_RUN		0x00000100
+#define SMSM_PWRC		0x00000200
+#define SMSM_TIMEWAIT		0x00000400
+#define SMSM_TIMEINIT		0x00000800
+#define SMSM_PWRC_EARLY_EXIT	0x00001000
+#define SMSM_WFPI		0x00002000
+#define SMSM_SLEEP		0x00004000
+#define SMSM_SLEEPEXIT		0x00008000
+#define SMSM_APPS_REBOOT	0x00020000
+#define SMSM_SYSTEM_POWER_DOWN	0x00040000
+#define SMSM_SYSTEM_REBOOT	0x00080000
+#define SMSM_SYSTEM_DOWNLOAD	0x00100000
+#define SMSM_PWRC_SUSPEND	0x00200000
+#define SMSM_APPS_SHUTDOWN	0x00400000
+#define SMSM_SMD_LOOPBACK	0x00800000
+#define SMSM_RUN_QUIET		0x01000000
+#define SMSM_MODEM_WAIT		0x02000000
+#define SMSM_MODEM_BREAK	0x04000000
+#define SMSM_MODEM_CONTINUE	0x08000000
+#define SMSM_UNKNOWN		0x80000000
 
 #define SMSM_WKUP_REASON_RPC	0x00000001
 #define SMSM_WKUP_REASON_INT	0x00000002
@@ -165,6 +179,26 @@ typedef enum
 	SMEM_ID_VENDOR1,
 	SMEM_ID_VENDOR2,
 	SMEM_HW_SW_BUILD_ID,
+	SMEM_SMD_BLOCK_PORT_BASE_ID,
+	SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
+	SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
+	SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
+	SMEM_SCLK_CONVERSION,
+	SMEM_SMD_SMSM_INTR_MUX,
+	SMEM_SMSM_CPU_INTR_MASK,
+	SMEM_APPS_DEM_SLAVE_DATA,
+	SMEM_QDSP6_DEM_SLAVE_DATA,
+	SMEM_CLKREGIM_BSP,
+	SMEM_CLKREGIM_SOURCES,
+	SMEM_SMD_FIFO_BASE_ID,
+	SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
+	SMEM_POWER_ON_STATUS_INFO,
+	SMEM_DAL_AREA,
+	SMEM_SMEM_LOG_POWER_IDX,
+	SMEM_SMEM_LOG_POWER_WRAP,
+	SMEM_SMEM_LOG_POWER_EVENTS,
+	SMEM_ERR_CRASH_LOG,
+	SMEM_ERR_F3_TRACE_LOG,	
 	SMEM_NUM_ITEMS,
 } smem_mem_type;