Commit 5c015726 authored by Devyn Liu's avatar Devyn Liu Committed by Andi Shyti

i2c: hisi: Optimized the value setting of maxwrite limit to fifo depth - 1

The driver finishes a write cycle by read the fifo tx full status
or write limit decrease to 0. The driver starts to write data to
the FIFO after the I2C FIFO almost empty interrupt is reported.
The threshold for FIFO almost empty interrupt is that the amount
of data in the FIFO is less than or equal to 1.
Reduce write maxwrite to the fifo depth - aempty interrupt
threshold. Limiting the number of data to be written at a time
to remaining fifo capacity.
Signed-off-by: default avatarDevyn Liu <liudingyuan@huawei.com>
Reviewed-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@kernel.org>
Signed-off-by: default avatarAndi Shyti <andi.shyti@kernel.org>
parent 7a7fd335
......@@ -266,7 +266,7 @@ static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr)
static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr)
{
int max_write = HISI_I2C_TX_FIFO_DEPTH;
int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH;
bool need_restart = false, last_msg;
struct i2c_msg *cur_msg;
u32 cmd, fifo_state;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment