Commit 5eb26c60 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Maxime Coquelin

ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
parent 0a8c739c
...@@ -21,8 +21,8 @@ Required properties: ...@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32" "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32" "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32" "sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32" "sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
......
...@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 { ...@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 { clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { ...@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 { clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>; clocks = <&clk_sysin>;
......
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