Commit 5f1695e0 authored by Greg Ungerer's avatar Greg Ungerer Committed by Jaroslav Kysela

[PATCH] add m68knommu/5282 start up code

Start up code for the M5282C3 Motorola ColdFire 5282 evaluation board.

New architecture and board for the m68knommu architecture branch, though
it is not very different to most existing ColdFire eval boards.
parent d7e69302
/*****************************************************************************/
/*
* crt0_ram.S -- startup code for MCF5282 ColdFire based MOTOROLA boards.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com).
*/
/*****************************************************************************/
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*****************************************************************************/
/*
* Motorola M5282C3 ColdFire eval board, chip select and memory setup.
*/
#define MEM_BASE 0x00000000 /* Memory base at address 0 */
#define VBR_BASE MEM_BASE /* Vector address */
#if defined(CONFIG_RAM16MB)
#define MEM_SIZE 0x01000000 /* Memory size 16Mb */
#elif defined(CONFIG_RAM8MB)
#define MEM_SIZE 0x00800000 /* Memory size 8Mb */
#else
#define MEM_SIZE 0x00400000 /* Memory size 4Mb */
#endif
/*****************************************************************************/
.global _start
.global _rambase
.global _ramvec
.global _ramstart
.global _ramend
/*****************************************************************************/
.data
/*
* Set up the usable of RAM stuff. Size of RAM is determined then
* an initial stack set up at the end.
*/
_rambase:
.long 0
_ramvec:
.long 0
_ramstart:
.long 0
_ramend:
.long 0
/*****************************************************************************/
.text
/*
* This is the codes first entry point. This is where it all
* begins...
*/
_start:
nop /* Filler */
move.w #0x2700, %sr /* No interrupts */
/*
* Setup VBR here, otherwise buserror remap will not work.
* if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
*
* bkr@cut.de 19990306
*
* Note: this is because dBUG points VBR to ROM, making vectors read
* only, so the bus trap can't be changed. (RS)
*/
move.l #VBR_BASE, %a7 /* Note VBR can't be read */
movec %a7, %VBR
move.l %a7, _ramvec /* Set up vector addr */
move.l %a7, _rambase /* Set up base RAM addr */
/*
* Set memory size.
*/
move.l #MEM_SIZE, %a0
move.l %a0, %d0 /* Mem end addr is in a0 */
move.l %d0, %sp /* Set up initial stack ptr */
move.l %d0, _ramend /* Set end ram addr */
/*
* Enable CPU internal cache.
*
* Cache is totally broken in first 5282 silicon.
* No point enabling it for now.
*/
#if 0
move.l #0x01000000, %d0
movec %d0, %CACR /* Invalidate cache */
nop
move.l #0x0000c000, %d0 /* Set SDRAM cached only */
movec %d0, %ACR0
move.l #0x00000000, %d0 /* No other regions cached */
movec %d0, %ACR1
move.l #0x00000000, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
#endif
/*
* Move ROM filesystem above bss :-)
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Set up destination */
move.l %a0, %a2 /* Copy of bss start */
move.l 8(%a0), %d0 /* Get size of ROMFS */
addq.l #8, %d0 /* Allow for rounding */
and.l #0xfffffffc, %d0 /* Whole words */
add.l %d0, %a0 /* Copy from end */
add.l %d0, %a1 /* Copy from end */
move.l %a1, _ramstart /* Set start of ram */
_copy_romfs:
move.l -(%a0), %d0 /* Copy dword */
move.l %d0, -(%a1)
cmp.l %a0, %a2 /* Check if at end */
bne _copy_romfs
/*
* Zero out the bss region.
*/
lea.l _sbss, %a0 /* Get start of bss */
lea.l _ebss, %a1 /* Get end of bss */
clr.l %d0 /* Set value */
_clear_bss:
move.l %d0, (%a0)+ /* Clear each word */
cmp.l %a0, %a1 /* Check if at end */
bne _clear_bss
/*
* Load the current thread pointer and stack.
*/
lea init_thread_union, %a0
lea 0x2000(%a0), %sp
/*
* Assember start up done, start code proper.
*/
jsr start_kernel /* Start Linux kernel */
_exit:
jmp _exit /* Should never get here */
/*****************************************************************************/
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