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Commit 5f371a81 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits 

Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.

v2: Handle DG1
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-10-ville.syrjala@linux.intel.com
parent e5abaab3
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Showing with 36 additions and 36 deletions
drivers/gpu/drm/i915/i915_irq.c
View file @ 5f371a81
...@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = { ...@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
}; };
static const u32 hpd_icp[HPD_NUM_PINS] = { static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C), [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1), [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2), [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3), [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
...@@ -153,10 +153,10 @@ static const u32 hpd_icp[HPD_NUM_PINS] = { ...@@ -153,10 +153,10 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
}; };
static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C), [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D), [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
}; };
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
...@@ -1076,13 +1076,13 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) ...@@ -1076,13 +1076,13 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{ {
switch (pin) { switch (pin) {
case HPD_PORT_A: case HPD_PORT_A:
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
case HPD_PORT_B: case HPD_PORT_B:
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
case HPD_PORT_C: case HPD_PORT_C:
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
case HPD_PORT_D: case HPD_PORT_D:
return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
default: default:
return false; return false;
} }
......
drivers/gpu/drm/i915/i915_reg.h
View file @ 5f371a81
...@@ -8350,26 +8350,26 @@ enum { ...@@ -8350,26 +8350,26 @@ enum {
/* south display engine interrupt: ICP/TGP */ /* south display engine interrupt: ICP/TGP */
#define SDE_GMBUS_ICP (1 << 23) #define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \ #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A)) SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \ #define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_1)) SDE_TC_HOTPLUG_ICP(TC_PORT_1))
#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \ #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
SDE_DDI_HOTPLUG_ICP(PORT_B) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A)) SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \ #define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
SDE_TC_HOTPLUG_ICP(TC_PORT_1)) SDE_TC_HOTPLUG_ICP(TC_PORT_1))
#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ #define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
SDE_DDI_HOTPLUG_ICP(PORT_C) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
SDE_DDI_HOTPLUG_ICP(PORT_B) | \ SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
SDE_DDI_HOTPLUG_ICP(PORT_A)) SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
#define SDEISR _MMIO(0xc4000) #define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004) #define SDEIMR _MMIO(0xc4004)
...@@ -8437,12 +8437,12 @@ enum { ...@@ -8437,12 +8437,12 @@ enum {
*/ */
#define SHOTPLUG_CTL_DDI _MMIO(0xc4030) #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port))) #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
#define SHOTPLUG_CTL_TC _MMIO(0xc4034) #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
...@@ -8452,22 +8452,22 @@ enum { ...@@ -8452,22 +8452,22 @@ enum {
#define SHPD_FILTER_CNT _MMIO(0xc4038) #define SHPD_FILTER_CNT _MMIO(0xc4038)
#define SHPD_FILTER_CNT_500_ADJ 0x001D9 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_4) | \ #define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_4) | \
ICP_TC_HPD_ENABLE(TC_PORT_3) | \ ICP_TC_HPD_ENABLE(TC_PORT_3) | \
ICP_TC_HPD_ENABLE(TC_PORT_2) | \ ICP_TC_HPD_ENABLE(TC_PORT_2) | \
ICP_TC_HPD_ENABLE(TC_PORT_1)) ICP_TC_HPD_ENABLE(TC_PORT_1))
#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_6) | \ #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_6) | \
ICP_TC_HPD_ENABLE(TC_PORT_5) | \ ICP_TC_HPD_ENABLE(TC_PORT_5) | \
ICP_TC_HPD_ENABLE_MASK) ICP_TC_HPD_ENABLE_MASK)
#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ #define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
#define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018 #define _PCH_DPLL_B 0xc6018
......
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