Commit 604542b8 authored by Joerg Roedel's avatar Joerg Roedel

Merge branches 'core', 'arm/omap', 'iommu/fixes', 'arm/tegra', 'arm/shmobile',...

Merge branches 'core', 'arm/omap', 'iommu/fixes', 'arm/tegra', 'arm/shmobile', 'arm/exynos', 'x86/vt-d' and 'x86/amd' into next
......@@ -105,11 +105,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.
config EXYNOS_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS platforms
config EXYNOS4_DEV_USB_OHCI
bool
help
......
......@@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
......
......@@ -24,7 +24,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
......@@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}
......
......@@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
......@@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
......
......@@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
#include "clock-exynos4.h"
......@@ -111,20 +110,30 @@ static struct clksrc_clk clksrcs[] = {
static struct clk init_clocks_off[] = {
{
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.15",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
......
......@@ -24,7 +24,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>
#include "common.h"
......@@ -859,73 +858,78 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 9)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 6)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
.ctrlbit = (0x3F << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
.ctrlbit = (0xF << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 8)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = &exynos5_clk_ip_acp_ctrl,
.ctrlbit = (1 << 7)
}
......
/* linux/arch/arm/mach-exynos/dev-sysmmu.c
*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/cpu.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/sysmmu.h>
static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
static struct sysmmu_platform_data platdata_##ipname = { \
.dbgname = #ipname, \
}; \
struct platform_device SYSMMU_PLATDEV(ipname) = \
{ \
.name = SYSMMU_DEVNAME_BASE, \
.id = devid, \
.dev = { \
.dma_mask = &exynos_sysmmu_dma_mask, \
.coherent_dma_mask = DMA_BIT_MASK(32), \
.platform_data = &platdata_##ipname, \
}, \
}
SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
SYSMMU_PLATFORM_DEVICE(tv, 2);
SYSMMU_PLATFORM_DEVICE(jpeg, 3);
SYSMMU_PLATFORM_DEVICE(rot, 4);
SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
SYSMMU_PLATFORM_DEVICE(fimc1, 6);
SYSMMU_PLATFORM_DEVICE(fimc2, 7);
SYSMMU_PLATFORM_DEVICE(fimc3, 8);
SYSMMU_PLATFORM_DEVICE(gsc0, 5);
SYSMMU_PLATFORM_DEVICE(gsc1, 6);
SYSMMU_PLATFORM_DEVICE(gsc2, 7);
SYSMMU_PLATFORM_DEVICE(gsc3, 8);
SYSMMU_PLATFORM_DEVICE(isp, 9);
SYSMMU_PLATFORM_DEVICE(fimd0, 10);
SYSMMU_PLATFORM_DEVICE(fimd1, 11);
SYSMMU_PLATFORM_DEVICE(camif0, 12);
SYSMMU_PLATFORM_DEVICE(camif1, 13);
SYSMMU_PLATFORM_DEVICE(2d, 14);
#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
#define SYSMMU_RESOURCE(core, ipname) \
static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
SYSMMU_RESOURCE(core, ipname) { \
DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
}
struct sysmmu_resource_map {
struct platform_device *pdev;
struct resource *res;
u32 rnum;
struct device *pdd;
char *clocknames;
};
#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME, \
}
#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
}
#ifdef CONFIG_EXYNOS_DEV_PD
#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME, \
.pdd = &exynos##core##_device_pd[pd].dev, \
}
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
.pdev = &SYSMMU_PLATDEV(ipname), \
.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
.pdd = &exynos##core##_device_pd[pd].dev, \
}
#else
#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
#endif /* CONFIG_EXYNOS_DEV_PD */
#ifdef CONFIG_ARCH_EXYNOS4
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
SYSMMU_RESOURCE(EXYNOS4, isp) {
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
};
static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
};
static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
};
static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
};
#endif /* CONFIG_ARCH_EXYNOS4 */
#ifdef CONFIG_ARCH_EXYNOS5
SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
SYSMMU_RESOURCE(EXYNOS5, isp) {
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
};
static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
SYSMMU_RESOURCE_MAPPING(5, rot, rot),
SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
};
#endif /* CONFIG_ARCH_EXYNOS5 */
static int __init init_sysmmu_platform_device(void)
{
int i, j;
struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
int nmap[2] = {0, 0};
#ifdef CONFIG_ARCH_EXYNOS5
if (soc_is_exynos5250()) {
resmap[0] = sysmmu_resmap5;
nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
nmap[1] = 0;
}
#endif
#ifdef CONFIG_ARCH_EXYNOS4
if (resmap[0] == NULL) {
resmap[0] = sysmmu_resmap4;
nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
}
if (soc_is_exynos4210()) {
resmap[1] = sysmmu_resmap4210;
nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
}
if (soc_is_exynos4412() || soc_is_exynos4212()) {
resmap[1] = sysmmu_resmap4212;
nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
}
#endif
for (j = 0; j < 2; j++) {
for (i = 0; i < nmap[j]; i++) {
struct sysmmu_resource_map *map;
struct sysmmu_platform_data *platdata;
map = &resmap[j][i];
map->pdev->dev.parent = map->pdd;
platdata = map->pdev->dev.platform_data;
platdata->clockname = map->clocknames;
if (platform_device_add_resources(map->pdev, map->res,
map->rnum)) {
pr_err("%s: Failed to add device resources for "
"%s.%d\n", __func__,
map->pdev->name, map->pdev->id);
continue;
}
if (platform_device_register(map->pdev)) {
pr_err("%s: Failed to register %s.%d\n",
__func__, map->pdev->name,
map->pdev->id);
}
}
}
return 0;
}
arch_initcall(init_sysmmu_platform_device);
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
#define _ARM_MACH_EXYNOS_SYSMMU_H_
struct sysmmu_platform_data {
char *dbgname;
/* comma(,) separated list of clock names for clock gating */
char *clockname;
};
#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
#define SYSMMU_CLOCK_NAME "sysmmu"
#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
#ifdef CONFIG_EXYNOS_DEV_SYSMMU
#include <linux/device.h>
struct platform_device;
#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
extern struct platform_device SYSMMU_PLATDEV(mfc_l);
extern struct platform_device SYSMMU_PLATDEV(mfc_r);
extern struct platform_device SYSMMU_PLATDEV(tv);
extern struct platform_device SYSMMU_PLATDEV(jpeg);
extern struct platform_device SYSMMU_PLATDEV(rot);
extern struct platform_device SYSMMU_PLATDEV(fimc0);
extern struct platform_device SYSMMU_PLATDEV(fimc1);
extern struct platform_device SYSMMU_PLATDEV(fimc2);
extern struct platform_device SYSMMU_PLATDEV(fimc3);
extern struct platform_device SYSMMU_PLATDEV(gsc0);
extern struct platform_device SYSMMU_PLATDEV(gsc1);
extern struct platform_device SYSMMU_PLATDEV(gsc2);
extern struct platform_device SYSMMU_PLATDEV(gsc3);
extern struct platform_device SYSMMU_PLATDEV(isp);
extern struct platform_device SYSMMU_PLATDEV(fimd0);
extern struct platform_device SYSMMU_PLATDEV(fimd1);
extern struct platform_device SYSMMU_PLATDEV(camif0);
extern struct platform_device SYSMMU_PLATDEV(camif1);
extern struct platform_device SYSMMU_PLATDEV(2d);
#ifdef CONFIG_IOMMU_API
static inline void platform_set_sysmmu(
struct device *sysmmu, struct device *dev)
{
dev->archdata.iommu = sysmmu;
}
#endif
#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
#endif
#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
......@@ -80,6 +80,40 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
"exynos-tmu", NULL),
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
"exynos-sysmmu.0", NULL), /* MFC_L */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
"exynos-sysmmu.1", NULL), /* MFC_R */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
"exynos-sysmmu.2", NULL), /* TV */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
"exynos-sysmmu.3", NULL), /* JPEG */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
"exynos-sysmmu.4", NULL), /* ROTATOR */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
"exynos-sysmmu.5", NULL), /* FIMC0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
"exynos-sysmmu.6", NULL), /* FIMC1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
"exynos-sysmmu.7", NULL), /* FIMC2 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
"exynos-sysmmu.8", NULL), /* FIMC3 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
"exynos-sysmmu.9", NULL), /* G2D(4210) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
"exynos-sysmmu.10", NULL), /* FIMD0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
{},
};
......
......@@ -104,6 +104,36 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
"exynos-tmu", NULL),
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
"exynos-sysmmu.0", "mfc"), /* MFC_L */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
"exynos-sysmmu.1", "mfc"), /* MFC_R */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
"exynos-sysmmu.2", NULL), /* TV */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
"exynos-sysmmu.3", "jpeg"), /* JPEG */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
"exynos-sysmmu.4", NULL), /* ROTATOR */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
"exynos-sysmmu.11", NULL), /* FIMD1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
"exynos-sysmmu.14", NULL), /* G2D */
{},
};
......
......@@ -28,6 +28,7 @@
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/sh_ipmmu.h>
#include <mach/dma-register.h>
#include <mach/r8a7740.h>
#include <mach/pm-rmobile.h>
......@@ -262,6 +263,37 @@ static struct platform_device cmt10_device = {
.num_resources = ARRAY_SIZE(cmt10_resources),
};
/* IPMMUI (an IPMMU module for ICB/LMB) */
static struct resource ipmmu_resources[] = {
[0] = {
.name = "IPMMUI",
.start = 0xfe951000,
.end = 0xfe9510ff,
.flags = IORESOURCE_MEM,
},
};
static const char * const ipmmu_dev_names[] = {
"sh_mobile_lcdc_fb.0",
"sh_mobile_lcdc_fb.1",
"sh_mobile_ceu.0",
};
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
.dev_names = ipmmu_dev_names,
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
};
static struct platform_device ipmmu_device = {
.name = "ipmmu",
.id = -1,
.dev = {
.platform_data = &ipmmu_platform_data,
},
.resource = ipmmu_resources,
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
......@@ -273,6 +305,7 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif7_device,
&scifb_device,
&cmt10_device,
&ipmmu_device,
};
/* DMA */
......
......@@ -33,6 +33,7 @@
#include <linux/sh_timer.h>
#include <linux/pm_domain.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/sh_ipmmu.h>
#include <mach/dma-register.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
......@@ -982,6 +983,43 @@ static struct platform_device spu1_device = {
.num_resources = ARRAY_SIZE(spu1_resources),
};
/* IPMMUI (an IPMMU module for ICB/LMB) */
static struct resource ipmmu_resources[] = {
[0] = {
.name = "IPMMUI",
.start = 0xfe951000,
.end = 0xfe9510ff,
.flags = IORESOURCE_MEM,
},
};
static const char * const ipmmu_dev_names[] = {
"sh_mobile_lcdc_fb.0",
"sh_mobile_lcdc_fb.1",
"sh_mobile_ceu.0",
"uio_pdrv_genirq.0",
"uio_pdrv_genirq.1",
"uio_pdrv_genirq.2",
"uio_pdrv_genirq.3",
"uio_pdrv_genirq.4",
"uio_pdrv_genirq.5",
};
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
.dev_names = ipmmu_dev_names,
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
};
static struct platform_device ipmmu_device = {
.name = "ipmmu",
.id = -1,
.dev = {
.platform_data = &ipmmu_platform_data,
},
.resource = ipmmu_resources,
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct platform_device *sh7372_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
......@@ -993,6 +1031,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
&cmt2_device,
&tmu00_device,
&tmu01_device,
&ipmmu_device,
};
static struct platform_device *sh7372_late_devices[] __initdata = {
......
......@@ -30,6 +30,7 @@
#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <linux/platform_data/sh_ipmmu.h>
#include <mach/dma-register.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
......@@ -754,6 +755,35 @@ static struct platform_device pmu_device = {
.resource = pmu_resources,
};
/* an IPMMU module for ICB */
static struct resource ipmmu_resources[] = {
[0] = {
.name = "IPMMU",
.start = 0xfe951000,
.end = 0xfe9510ff,
.flags = IORESOURCE_MEM,
},
};
static const char * const ipmmu_dev_names[] = {
"sh_mobile_lcdc_fb.0",
};
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
.dev_names = ipmmu_dev_names,
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
};
static struct platform_device ipmmu_device = {
.name = "ipmmu",
.id = -1,
.dev = {
.platform_data = &ipmmu_platform_data,
},
.resource = ipmmu_resources,
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct platform_device *sh73a0_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
......@@ -767,6 +797,7 @@ static struct platform_device *sh73a0_early_devices[] __initdata = {
&cmt10_device,
&tmu00_device,
&tmu01_device,
&ipmmu_device,
};
static struct platform_device *sh73a0_late_devices[] __initdata = {
......
......@@ -158,7 +158,7 @@ config TEGRA_IOMMU_GART
config TEGRA_IOMMU_SMMU
bool "Tegra SMMU IOMMU Support"
depends on ARCH_TEGRA_3x_SOC && TEGRA_AHB
depends on ARCH_TEGRA && TEGRA_AHB
select IOMMU_API
help
Enables support for remapping discontiguous physical memory
......@@ -187,4 +187,78 @@ config EXYNOS_IOMMU_DEBUG
Say N unless you need kernel log message for IOMMU debugging
config SHMOBILE_IPMMU
bool
config SHMOBILE_IPMMU_TLB
bool
config SHMOBILE_IOMMU
bool "IOMMU for Renesas IPMMU/IPMMUI"
default n
depends on (ARM && ARCH_SHMOBILE)
select IOMMU_API
select ARM_DMA_USE_IOMMU
select SHMOBILE_IPMMU
select SHMOBILE_IPMMU_TLB
help
Support for Renesas IPMMU/IPMMUI. This option enables
remapping of DMA memory accesses from all of the IP blocks
on the ICB.
Warning: Drivers (including userspace drivers of UIO
devices) of the IP blocks on the ICB *must* use addresses
allocated from the IPMMU (iova) for DMA with this option
enabled.
If unsure, say N.
choice
prompt "IPMMU/IPMMUI address space size"
default SHMOBILE_IOMMU_ADDRSIZE_2048MB
depends on SHMOBILE_IOMMU
help
This option sets IPMMU/IPMMUI address space size by
adjusting the 1st level page table size. The page table size
is calculated as follows:
page table size = number of page table entries * 4 bytes
number of page table entries = address space size / 1 MiB
For example, when the address space size is 2048 MiB, the
1st level page table size is 8192 bytes.
config SHMOBILE_IOMMU_ADDRSIZE_2048MB
bool "2 GiB"
config SHMOBILE_IOMMU_ADDRSIZE_1024MB
bool "1 GiB"
config SHMOBILE_IOMMU_ADDRSIZE_512MB
bool "512 MiB"
config SHMOBILE_IOMMU_ADDRSIZE_256MB
bool "256 MiB"
config SHMOBILE_IOMMU_ADDRSIZE_128MB
bool "128 MiB"
config SHMOBILE_IOMMU_ADDRSIZE_64MB
bool "64 MiB"
config SHMOBILE_IOMMU_ADDRSIZE_32MB
bool "32 MiB"
endchoice
config SHMOBILE_IOMMU_L1SIZE
int
default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB
default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB
default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB
default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB
default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB
default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB
default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB
endif # IOMMU_SUPPORT
......@@ -13,3 +13,5 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
obj-$(CONFIG_SHMOBILE_IOMMU) += shmobile-iommu.o
obj-$(CONFIG_SHMOBILE_IPMMU) += shmobile-ipmmu.o
......@@ -3187,8 +3187,7 @@ int __init amd_iommu_init_dma_ops(void)
free_domains:
for_each_iommu(iommu) {
if (iommu->default_dom)
dma_ops_domain_free(iommu->default_dom);
dma_ops_domain_free(iommu->default_dom);
}
return ret;
......
......@@ -1876,11 +1876,6 @@ static int amd_iommu_init_dma(void)
struct amd_iommu *iommu;
int ret;
init_device_table_dma();
for_each_iommu(iommu)
iommu_flush_all_caches(iommu);
if (iommu_pass_through)
ret = amd_iommu_init_passthrough();
else
......@@ -1889,6 +1884,11 @@ static int amd_iommu_init_dma(void)
if (ret)
return ret;
init_device_table_dma();
for_each_iommu(iommu)
iommu_flush_all_caches(iommu);
amd_iommu_init_api();
amd_iommu_init_notifier();
......
......@@ -1040,7 +1040,7 @@ int dmar_enable_qi(struct intel_iommu *iommu)
qi->desc = page_address(desc_page);
qi->desc_status = kmalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC);
if (!qi->desc_status) {
free_page((unsigned long) qi->desc);
kfree(qi);
......
......@@ -511,7 +511,7 @@ int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
return ret;
}
bool exynos_sysmmu_disable(struct device *dev)
static bool exynos_sysmmu_disable(struct device *dev)
{
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
bool disabled;
......
......@@ -734,7 +734,8 @@ int iommu_map(struct iommu_domain *domain, unsigned long iova,
size_t orig_size = size;
int ret = 0;
if (unlikely(domain->ops->map == NULL))
if (unlikely(domain->ops->unmap == NULL ||
domain->ops->pgsize_bitmap == 0UL))
return -ENODEV;
/* find out the minimum page size supported */
......@@ -808,7 +809,8 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
size_t unmapped_page, unmapped = 0;
unsigned int min_pagesz;
if (unlikely(domain->ops->unmap == NULL))
if (unlikely(domain->ops->unmap == NULL ||
domain->ops->pgsize_bitmap == 0UL))
return -ENODEV;
/* find out the minimum page size supported */
......@@ -850,6 +852,26 @@ size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
}
EXPORT_SYMBOL_GPL(iommu_unmap);
int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,
phys_addr_t paddr, u64 size)
{
if (unlikely(domain->ops->domain_window_enable == NULL))
return -ENODEV;
return domain->ops->domain_window_enable(domain, wnd_nr, paddr, size);
}
EXPORT_SYMBOL_GPL(iommu_domain_window_enable);
void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr)
{
if (unlikely(domain->ops->domain_window_disable == NULL))
return;
return domain->ops->domain_window_disable(domain, wnd_nr);
}
EXPORT_SYMBOL_GPL(iommu_domain_window_disable);
static int __init iommu_init(void)
{
iommu_group_kset = kset_create_and_add("iommu_groups",
......@@ -861,19 +883,34 @@ static int __init iommu_init(void)
return 0;
}
subsys_initcall(iommu_init);
arch_initcall(iommu_init);
int iommu_domain_get_attr(struct iommu_domain *domain,
enum iommu_attr attr, void *data)
{
struct iommu_domain_geometry *geometry;
bool *paging;
int ret = 0;
u32 *count;
switch (attr) {
case DOMAIN_ATTR_GEOMETRY:
geometry = data;
*geometry = domain->geometry;
break;
case DOMAIN_ATTR_PAGING:
paging = data;
*paging = (domain->ops->pgsize_bitmap != 0UL);
break;
case DOMAIN_ATTR_WINDOWS:
count = data;
if (domain->ops->domain_get_windows != NULL)
*count = domain->ops->domain_get_windows(domain);
else
ret = -ENODEV;
break;
default:
if (!domain->ops->domain_get_attr)
......@@ -889,9 +926,26 @@ EXPORT_SYMBOL_GPL(iommu_domain_get_attr);
int iommu_domain_set_attr(struct iommu_domain *domain,
enum iommu_attr attr, void *data)
{
if (!domain->ops->domain_set_attr)
return -EINVAL;
int ret = 0;
u32 *count;
return domain->ops->domain_set_attr(domain, attr, data);
switch (attr) {
case DOMAIN_ATTR_WINDOWS:
count = data;
if (domain->ops->domain_set_windows != NULL)
ret = domain->ops->domain_set_windows(domain, *count);
else
ret = -ENODEV;
break;
default:
if (domain->ops->domain_set_attr == NULL)
return -EINVAL;
ret = domain->ops->domain_set_attr(domain, attr, data);
}
return ret;
}
EXPORT_SYMBOL_GPL(iommu_domain_set_attr);
......@@ -146,7 +146,7 @@ static int iommu_enable(struct omap_iommu *obj)
struct platform_device *pdev = to_platform_device(obj->dev);
struct iommu_platform_data *pdata = pdev->dev.platform_data;
if (!obj || !pdata)
if (!pdata)
return -EINVAL;
if (!arch_iommu)
......@@ -172,7 +172,7 @@ static void iommu_disable(struct omap_iommu *obj)
struct platform_device *pdev = to_platform_device(obj->dev);
struct iommu_platform_data *pdata = pdev->dev.platform_data;
if (!obj || !pdata)
if (!pdata)
return;
arch_iommu->disable(obj);
......
This diff is collapsed.
/*
* IPMMU/IPMMUI
* Copyright (C) 2012 Hideki EIRAKU
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/err.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/platform_data/sh_ipmmu.h>
#include "shmobile-ipmmu.h"
#define IMCTR1 0x000
#define IMCTR2 0x004
#define IMASID 0x010
#define IMTTBR 0x014
#define IMTTBCR 0x018
#define IMCTR1_TLBEN (1 << 0)
#define IMCTR1_FLUSH (1 << 1)
static void ipmmu_reg_write(struct shmobile_ipmmu *ipmmu, unsigned long reg_off,
unsigned long data)
{
iowrite32(data, ipmmu->ipmmu_base + reg_off);
}
void ipmmu_tlb_flush(struct shmobile_ipmmu *ipmmu)
{
if (!ipmmu)
return;
mutex_lock(&ipmmu->flush_lock);
if (ipmmu->tlb_enabled)
ipmmu_reg_write(ipmmu, IMCTR1, IMCTR1_FLUSH | IMCTR1_TLBEN);
else
ipmmu_reg_write(ipmmu, IMCTR1, IMCTR1_FLUSH);
mutex_unlock(&ipmmu->flush_lock);
}
void ipmmu_tlb_set(struct shmobile_ipmmu *ipmmu, unsigned long phys, int size,
int asid)
{
if (!ipmmu)
return;
mutex_lock(&ipmmu->flush_lock);
switch (size) {
default:
ipmmu->tlb_enabled = 0;
break;
case 0x2000:
ipmmu_reg_write(ipmmu, IMTTBCR, 1);
ipmmu->tlb_enabled = 1;
break;
case 0x1000:
ipmmu_reg_write(ipmmu, IMTTBCR, 2);
ipmmu->tlb_enabled = 1;
break;
case 0x800:
ipmmu_reg_write(ipmmu, IMTTBCR, 3);
ipmmu->tlb_enabled = 1;
break;
case 0x400:
ipmmu_reg_write(ipmmu, IMTTBCR, 4);
ipmmu->tlb_enabled = 1;
break;
case 0x200:
ipmmu_reg_write(ipmmu, IMTTBCR, 5);
ipmmu->tlb_enabled = 1;
break;
case 0x100:
ipmmu_reg_write(ipmmu, IMTTBCR, 6);
ipmmu->tlb_enabled = 1;
break;
case 0x80:
ipmmu_reg_write(ipmmu, IMTTBCR, 7);
ipmmu->tlb_enabled = 1;
break;
}
ipmmu_reg_write(ipmmu, IMTTBR, phys);
ipmmu_reg_write(ipmmu, IMASID, asid);
mutex_unlock(&ipmmu->flush_lock);
}
static int ipmmu_probe(struct platform_device *pdev)
{
struct shmobile_ipmmu *ipmmu;
struct resource *res;
struct shmobile_ipmmu_platform_data *pdata = pdev->dev.platform_data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "cannot get platform resources\n");
return -ENOENT;
}
ipmmu = devm_kzalloc(&pdev->dev, sizeof(*ipmmu), GFP_KERNEL);
if (!ipmmu) {
dev_err(&pdev->dev, "cannot allocate device data\n");
return -ENOMEM;
}
mutex_init(&ipmmu->flush_lock);
ipmmu->dev = &pdev->dev;
ipmmu->ipmmu_base = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (!ipmmu->ipmmu_base) {
dev_err(&pdev->dev, "ioremap_nocache failed\n");
return -ENOMEM;
}
ipmmu->dev_names = pdata->dev_names;
ipmmu->num_dev_names = pdata->num_dev_names;
platform_set_drvdata(pdev, ipmmu);
ipmmu_reg_write(ipmmu, IMCTR1, 0x0); /* disable TLB */
ipmmu_reg_write(ipmmu, IMCTR2, 0x0); /* disable PMB */
ipmmu_iommu_init(ipmmu);
return 0;
}
static struct platform_driver ipmmu_driver = {
.probe = ipmmu_probe,
.driver = {
.owner = THIS_MODULE,
.name = "ipmmu",
},
};
static int __init ipmmu_init(void)
{
return platform_driver_register(&ipmmu_driver);
}
subsys_initcall(ipmmu_init);
/* shmobile-ipmmu.h
*
* Copyright (C) 2012 Hideki EIRAKU
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __SHMOBILE_IPMMU_H__
#define __SHMOBILE_IPMMU_H__
struct shmobile_ipmmu {
struct device *dev;
void __iomem *ipmmu_base;
int tlb_enabled;
struct mutex flush_lock;
const char * const *dev_names;
unsigned int num_dev_names;
};
#ifdef CONFIG_SHMOBILE_IPMMU_TLB
void ipmmu_tlb_flush(struct shmobile_ipmmu *ipmmu);
void ipmmu_tlb_set(struct shmobile_ipmmu *ipmmu, unsigned long phys, int size,
int asid);
int ipmmu_iommu_init(struct shmobile_ipmmu *ipmmu);
#else
static inline int ipmmu_iommu_init(struct shmobile_ipmmu *ipmmu)
{
return -EINVAL;
}
#endif
#endif /* __SHMOBILE_IPMMU_H__ */
......@@ -430,13 +430,11 @@ const struct dev_pm_ops tegra_gart_pm_ops = {
.resume = tegra_gart_resume,
};
#ifdef CONFIG_OF
static struct of_device_id tegra_gart_of_match[] = {
{ .compatible = "nvidia,tegra20-gart", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_gart_of_match);
#endif
static struct platform_driver tegra_gart_driver = {
.probe = tegra_gart_probe,
......@@ -445,7 +443,7 @@ static struct platform_driver tegra_gart_driver = {
.owner = THIS_MODULE,
.name = "tegra-gart",
.pm = &tegra_gart_pm_ops,
.of_match_table = of_match_ptr(tegra_gart_of_match),
.of_match_table = tegra_gart_of_match,
},
};
......
/*
* IOMMU API for SMMU in Tegra30
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
......@@ -293,7 +293,11 @@ struct smmu_debugfs_info {
* Per SMMU device - IOMMU device
*/
struct smmu_device {
void __iomem *regs[NUM_SMMU_REG_BANKS];
void __iomem *regbase; /* register offset base */
void __iomem **regs; /* register block start address array */
void __iomem **rege; /* register block end address array */
int nregs; /* number of register blocks */
unsigned long iovmm_base; /* remappable base address */
unsigned long page_count; /* total remappable size */
spinlock_t lock;
......@@ -323,38 +327,37 @@ static struct smmu_device *smmu_handle; /* unique for a system */
/*
* SMMU register accessors
*/
static bool inline smmu_valid_reg(struct smmu_device *smmu,
void __iomem *addr)
{
int i;
for (i = 0; i < smmu->nregs; i++) {
if (addr < smmu->regs[i])
break;
if (addr <= smmu->rege[i])
return true;
}
return false;
}
static inline u32 smmu_read(struct smmu_device *smmu, size_t offs)
{
BUG_ON(offs < 0x10);
if (offs < 0x3c)
return readl(smmu->regs[0] + offs - 0x10);
BUG_ON(offs < 0x1f0);
if (offs < 0x200)
return readl(smmu->regs[1] + offs - 0x1f0);
BUG_ON(offs < 0x228);
if (offs < 0x284)
return readl(smmu->regs[2] + offs - 0x228);
BUG();
void __iomem *addr = smmu->regbase + offs;
BUG_ON(!smmu_valid_reg(smmu, addr));
return readl(addr);
}
static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs)
{
BUG_ON(offs < 0x10);
if (offs < 0x3c) {
writel(val, smmu->regs[0] + offs - 0x10);
return;
}
BUG_ON(offs < 0x1f0);
if (offs < 0x200) {
writel(val, smmu->regs[1] + offs - 0x1f0);
return;
}
BUG_ON(offs < 0x228);
if (offs < 0x284) {
writel(val, smmu->regs[2] + offs - 0x228);
return;
}
BUG();
void __iomem *addr = smmu->regbase + offs;
BUG_ON(!smmu_valid_reg(smmu, addr));
writel(val, addr);
}
#define VA_PAGE_TO_PA(va, page) \
......@@ -1170,7 +1173,13 @@ static int tegra_smmu_probe(struct platform_device *pdev)
return -ENOMEM;
}
for (i = 0; i < ARRAY_SIZE(smmu->regs); i++) {
smmu->nregs = pdev->num_resources;
smmu->regs = devm_kzalloc(dev, 2 * smmu->nregs * sizeof(*smmu->regs),
GFP_KERNEL);
smmu->rege = smmu->regs + smmu->nregs;
if (!smmu->regs)
return -ENOMEM;
for (i = 0; i < smmu->nregs; i++) {
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
......@@ -1179,7 +1188,10 @@ static int tegra_smmu_probe(struct platform_device *pdev)
smmu->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
if (!smmu->regs[i])
return -EBUSY;
smmu->rege[i] = smmu->regs[i] + resource_size(res) - 1;
}
/* Same as "mc" 1st regiter block start address */
smmu->regbase = (void __iomem *)((u32)smmu->regs[0] & PAGE_MASK);
err = of_get_dma_window(dev->of_node, NULL, 0, NULL, &base, &size);
if (err)
......@@ -1216,6 +1228,7 @@ static int tegra_smmu_probe(struct platform_device *pdev)
as->pte_attr = _PTE_ATTR;
spin_lock_init(&as->lock);
spin_lock_init(&as->client_lock);
INIT_LIST_HEAD(&as->client);
}
spin_lock_init(&smmu->lock);
......@@ -1254,13 +1267,11 @@ const struct dev_pm_ops tegra_smmu_pm_ops = {
.resume = tegra_smmu_resume,
};
#ifdef CONFIG_OF
static struct of_device_id tegra_smmu_of_match[] = {
{ .compatible = "nvidia,tegra30-smmu", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_smmu_of_match);
#endif
static struct platform_driver tegra_smmu_driver = {
.probe = tegra_smmu_probe,
......@@ -1269,7 +1280,7 @@ static struct platform_driver tegra_smmu_driver = {
.owner = THIS_MODULE,
.name = "tegra-smmu",
.pm = &tegra_smmu_pm_ops,
.of_match_table = of_match_ptr(tegra_smmu_of_match),
.of_match_table = tegra_smmu_of_match,
},
};
......
......@@ -58,8 +58,10 @@ struct iommu_domain {
#define IOMMU_CAP_INTR_REMAP 0x2 /* isolates device intrs */
enum iommu_attr {
DOMAIN_ATTR_MAX,
DOMAIN_ATTR_GEOMETRY,
DOMAIN_ATTR_PAGING,
DOMAIN_ATTR_WINDOWS,
DOMAIN_ATTR_MAX,
};
#ifdef CONFIG_IOMMU_API
......@@ -100,6 +102,16 @@ struct iommu_ops {
enum iommu_attr attr, void *data);
int (*domain_set_attr)(struct iommu_domain *domain,
enum iommu_attr attr, void *data);
/* Window handling functions */
int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr,
phys_addr_t paddr, u64 size);
void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr);
/* Set the numer of window per domain */
int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count);
/* Get the numer of window per domain */
u32 (*domain_get_windows)(struct iommu_domain *domain);
unsigned long pgsize_bitmap;
};
......@@ -157,6 +169,10 @@ extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr,
extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr,
void *data);
/* Window handling function prototypes */
extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr,
phys_addr_t offset, u64 size);
extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr);
/**
* report_iommu_fault() - report about an IOMMU fault to the IOMMU framework
* @domain: the iommu domain where the fault has happened
......@@ -239,6 +255,18 @@ static inline int iommu_unmap(struct iommu_domain *domain, unsigned long iova,
return -ENODEV;
}
static inline int iommu_domain_window_enable(struct iommu_domain *domain,
u32 wnd_nr, phys_addr_t paddr,
u64 size)
{
return -ENODEV;
}
static inline void iommu_domain_window_disable(struct iommu_domain *domain,
u32 wnd_nr)
{
}
static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
unsigned long iova)
{
......
/* sh_ipmmu.h
*
* Copyright (C) 2012 Hideki EIRAKU
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __SH_IPMMU_H__
#define __SH_IPMMU_H__
struct shmobile_ipmmu_platform_data {
const char * const *dev_names;
unsigned int num_dev_names;
};
#endif /* __SH_IPMMU_H__ */
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