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Commit 61fbeb5d authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Mark Brown
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ASoC: remove sirf prima/atlas drivers 

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarBarry Song <baohua@kernel.org>
Link: https://lore.kernel.org/r/20210120162553.21666-2-arnd@kernel.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6b050d45
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Documentation/devicetree/bindings/sound/sirf-audio-codec.txt deleted 100644 → 0
View file @ 6b050d45
SiRF internal audio CODEC
Required properties:
- compatible : "sirf,atlas6-audio-codec" or "sirf,prima2-audio-codec"
- reg : the register address of the device.
- clocks: the clock of SiRF internal audio codec
Example:
audiocodec: audiocodec@b0040000 {
compatible = "sirf,atlas6-audio-codec";
reg = <0xb0040000 0x10000>;
clocks = <&clks 27>;
};
Documentation/devicetree/bindings/sound/sirf-usp.txt deleted 100644 → 0
View file @ 6b050d45
* SiRF SoC USP module
Required properties:
- compatible: "sirf,prima2-usp-pcm"
- reg: Base address and size entries:
- dmas: List of DMA controller phandle and DMA request line ordered pairs.
- dma-names: Identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
One of the DMA channels will be responsible for transmission (should be
named "tx") and one for reception (should be named "rx").
- clocks: USP controller clock source
- pinctrl-names: Must contain a "default" entry.
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
Example:
usp0: usp@b0080000 {
compatible = "sirf,prima2-usp-pcm";
reg = <0xb0080000 0x10000>;
clocks = <&clks 28>;
dmas = <&dmac1 1>, <&dmac1 2>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&usp0_only_utfs_pins_a>;
};
sound/soc/Kconfig
View file @ 61fbeb5d
......@@ -62,7 +62,6 @@ source "sound/soc/qcom/Kconfig"
source "sound/soc/rockchip/Kconfig"
source "sound/soc/samsung/Kconfig"
source "sound/soc/sh/Kconfig"
source "sound/soc/sirf/Kconfig"
source "sound/soc/sof/Kconfig"
source "sound/soc/spear/Kconfig"
source "sound/soc/sprd/Kconfig"
......
sound/soc/Makefile
View file @ 61fbeb5d
......@@ -45,7 +45,6 @@ obj-$(CONFIG_SND_SOC) += qcom/
obj-$(CONFIG_SND_SOC) += rockchip/
obj-$(CONFIG_SND_SOC) += samsung/
obj-$(CONFIG_SND_SOC) += sh/
obj-$(CONFIG_SND_SOC) += sirf/
obj-$(CONFIG_SND_SOC) += sof/
obj-$(CONFIG_SND_SOC) += spear/
obj-$(CONFIG_SND_SOC) += sprd/
......
sound/soc/codecs/Makefile
View file @ 61fbeb5d
......@@ -201,7 +201,6 @@ snd-soc-sigmadsp-objs := sigmadsp.o
snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o
snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o
snd-soc-si476x-objs := si476x.o
snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o
snd-soc-spdif-tx-objs := spdif_transmitter.o
snd-soc-spdif-rx-objs := spdif_receiver.o
snd-soc-ssm2305-objs := ssm2305.o
......@@ -516,7 +515,6 @@ obj-$(CONFIG_SND_SOC_SIGMADSP_I2C) += snd-soc-sigmadsp-i2c.o
obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP) += snd-soc-sigmadsp-regmap.o
obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif-rx.o snd-soc-spdif-tx.o
obj-$(CONFIG_SND_SOC_SIRF_AUDIO_CODEC) += sirf-audio-codec.o
obj-$(CONFIG_SND_SOC_SSM2305) += snd-soc-ssm2305.o
obj-$(CONFIG_SND_SOC_SSM2518) += snd-soc-ssm2518.o
obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
......
sound/soc/codecs/sirf-audio-codec.c deleted 100644 → 0
View file @ 6b050d45
This diff is collapsed.
sound/soc/sirf/Kconfig deleted 100644 → 0
View file @ 6b050d45
# SPDX-License-Identifier: GPL-2.0-only
config SND_SOC_SIRF
tristate "SoC Audio for the SiRF SoC chips"
depends on ARCH_SIRF || COMPILE_TEST
select SND_SOC_GENERIC_DMAENGINE_PCM
config SND_SOC_SIRF_AUDIO
tristate "SoC Audio support for SiRF internal audio codec"
depends on SND_SOC_SIRF
select SND_SOC_SIRF_AUDIO_CODEC
select SND_SOC_SIRF_AUDIO_PORT
config SND_SOC_SIRF_AUDIO_PORT
select REGMAP_MMIO
tristate
config SND_SOC_SIRF_USP
tristate "SoC Audio (I2S protocol) for SiRF SoC USP interface"
depends on SND_SOC_SIRF
select REGMAP_MMIO
tristate
sound/soc/sirf/Makefile deleted 100644 → 0
View file @ 6b050d45
# SPDX-License-Identifier: GPL-2.0
snd-soc-sirf-audio-objs := sirf-audio.o
snd-soc-sirf-audio-port-objs := sirf-audio-port.o
snd-soc-sirf-usp-objs := sirf-usp.o
obj-$(CONFIG_SND_SOC_SIRF_AUDIO) += snd-soc-sirf-audio.o
obj-$(CONFIG_SND_SOC_SIRF_AUDIO_PORT) += snd-soc-sirf-audio-port.o
obj-$(CONFIG_SND_SOC_SIRF_USP) += snd-soc-sirf-usp.o
sound/soc/sirf/sirf-audio-port.c deleted 100644 → 0
View file @ 6b050d45
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SiRF Audio port driver
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
struct sirf_audio_port {
struct regmap *regmap;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct snd_dmaengine_dai_dma_data capture_dma_data;
};
static int sirf_audio_port_dai_probe(struct snd_soc_dai *dai)
{
struct sirf_audio_port *port = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &port->playback_dma_data,
&port->capture_dma_data);
return 0;
}
static struct snd_soc_dai_driver sirf_audio_port_dai = {
.probe = sirf_audio_port_dai_probe,
.name = "sirf-audio-port",
.id = 0,
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
};
static const struct snd_soc_component_driver sirf_audio_port_component = {
.name = "sirf-audio-port",
};
static int sirf_audio_port_probe(struct platform_device *pdev)
{
int ret;
struct sirf_audio_port *port;
port = devm_kzalloc(&pdev->dev,
sizeof(struct sirf_audio_port), GFP_KERNEL);
if (!port)
return -ENOMEM;
ret = devm_snd_soc_register_component(&pdev->dev,
&sirf_audio_port_component, &sirf_audio_port_dai, 1);
if (ret)
return ret;
platform_set_drvdata(pdev, port);
return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
}
static const struct of_device_id sirf_audio_port_of_match[] = {
{ .compatible = "sirf,audio-port", },
{}
};
MODULE_DEVICE_TABLE(of, sirf_audio_port_of_match);
static struct platform_driver sirf_audio_port_driver = {
.driver = {
.name = "sirf-audio-port",
.of_match_table = sirf_audio_port_of_match,
},
.probe = sirf_audio_port_probe,
};
module_platform_driver(sirf_audio_port_driver);
MODULE_DESCRIPTION("SiRF Audio Port driver");
MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
MODULE_LICENSE("GPL v2");
sound/soc/sirf/sirf-audio.c deleted 100644 → 0
View file @ 6b050d45
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SiRF audio card driver
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
struct sirf_audio_card {
unsigned int gpio_hp_pa;
unsigned int gpio_spk_pa;
};
static int sirf_audio_hp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *ctrl, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct snd_soc_card *card = dapm->card;
struct sirf_audio_card *sirf_audio_card = snd_soc_card_get_drvdata(card);
int on = !SND_SOC_DAPM_EVENT_OFF(event);
if (gpio_is_valid(sirf_audio_card->gpio_hp_pa))
gpio_set_value(sirf_audio_card->gpio_hp_pa, on);
return 0;
}
static int sirf_audio_spk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *ctrl, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct snd_soc_card *card = dapm->card;
struct sirf_audio_card *sirf_audio_card = snd_soc_card_get_drvdata(card);
int on = !SND_SOC_DAPM_EVENT_OFF(event);
if (gpio_is_valid(sirf_audio_card->gpio_spk_pa))
gpio_set_value(sirf_audio_card->gpio_spk_pa, on);
return 0;
}
static const struct snd_soc_dapm_widget sirf_audio_dapm_widgets[] = {
SND_SOC_DAPM_HP("Hp", sirf_audio_hp_event),
SND_SOC_DAPM_SPK("Ext Spk", sirf_audio_spk_event),
SND_SOC_DAPM_MIC("Ext Mic", NULL),
};
static const struct snd_soc_dapm_route intercon[] = {
{"Hp", NULL, "HPOUTL"},
{"Hp", NULL, "HPOUTR"},
{"Ext Spk", NULL, "SPKOUT"},
{"MICIN1", NULL, "Mic Bias"},
{"Mic Bias", NULL, "Ext Mic"},
};
/* Digital audio interface glue - connects codec <--> CPU */
SND_SOC_DAILINK_DEFS(sirf,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "sirf-audio-codec")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link sirf_audio_dai_link[] = {
{
.name = "SiRF audio card",
.stream_name = "SiRF audio HiFi",
SND_SOC_DAILINK_REG(sirf),
},
};
/* Audio machine driver */
static struct snd_soc_card snd_soc_sirf_audio_card = {
.name = "SiRF audio card",
.owner = THIS_MODULE,
.dai_link = sirf_audio_dai_link,
.num_links = ARRAY_SIZE(sirf_audio_dai_link),
.dapm_widgets = sirf_audio_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sirf_audio_dapm_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
};
static int sirf_audio_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &snd_soc_sirf_audio_card;
struct sirf_audio_card *sirf_audio_card;
int ret;
sirf_audio_card = devm_kzalloc(&pdev->dev, sizeof(struct sirf_audio_card),
GFP_KERNEL);
if (sirf_audio_card == NULL)
return -ENOMEM;
sirf_audio_dai_link[0].cpus->of_node =
of_parse_phandle(pdev->dev.of_node, "sirf,audio-platform", 0);
sirf_audio_dai_link[0].platforms->of_node =
of_parse_phandle(pdev->dev.of_node, "sirf,audio-platform", 0);
sirf_audio_dai_link[0].codecs->of_node =
of_parse_phandle(pdev->dev.of_node, "sirf,audio-codec", 0);
sirf_audio_card->gpio_spk_pa = of_get_named_gpio(pdev->dev.of_node,
"spk-pa-gpios", 0);
sirf_audio_card->gpio_hp_pa = of_get_named_gpio(pdev->dev.of_node,
"hp-pa-gpios", 0);
if (gpio_is_valid(sirf_audio_card->gpio_spk_pa)) {
ret = devm_gpio_request_one(&pdev->dev,
sirf_audio_card->gpio_spk_pa,
GPIOF_OUT_INIT_LOW, "SPA_PA_SD");
if (ret) {
dev_err(&pdev->dev,
"Failed to request GPIO_%d for reset: %d\n",
sirf_audio_card->gpio_spk_pa, ret);
return ret;
}
}
if (gpio_is_valid(sirf_audio_card->gpio_hp_pa)) {
ret = devm_gpio_request_one(&pdev->dev,
sirf_audio_card->gpio_hp_pa,
GPIOF_OUT_INIT_LOW, "HP_PA_SD");
if (ret) {
dev_err(&pdev->dev,
"Failed to request GPIO_%d for reset: %d\n",
sirf_audio_card->gpio_hp_pa, ret);
return ret;
}
}
card->dev = &pdev->dev;
snd_soc_card_set_drvdata(card, sirf_audio_card);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
return ret;
}
static const struct of_device_id sirf_audio_of_match[] = {
{.compatible = "sirf,sirf-audio-card", },
{ },
};
MODULE_DEVICE_TABLE(of, sirf_audio_of_match);
static struct platform_driver sirf_audio_driver = {
.driver = {
.name = "sirf-audio-card",
.pm = &snd_soc_pm_ops,
.of_match_table = sirf_audio_of_match,
},
.probe = sirf_audio_probe,
};
module_platform_driver(sirf_audio_driver);
MODULE_AUTHOR("RongJun Ying <RongJun.Ying@csr.com>");
MODULE_DESCRIPTION("ALSA SoC SIRF audio card driver");
MODULE_LICENSE("GPL v2");
sound/soc/sirf/sirf-usp.c deleted 100644 → 0
View file @ 6b050d45
This diff is collapsed.
sound/soc/sirf/sirf-usp.h deleted 100644 → 0
View file @ 6b050d45
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* arch/arm/mach-prima2/include/mach/sirfsoc_usp.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#ifndef _SIRF_USP_H
#define _SIRF_USP_H
/* USP Registers */
#define USP_MODE1 0x00
#define USP_MODE2 0x04
#define USP_TX_FRAME_CTRL 0x08
#define USP_RX_FRAME_CTRL 0x0C
#define USP_TX_RX_ENABLE 0x10
#define USP_INT_ENABLE 0x14
#define USP_INT_STATUS 0x18
#define USP_PIN_IO_DATA 0x1C
#define USP_RISC_DSP_MODE 0x20
#define USP_AYSNC_PARAM_REG 0x24
#define USP_IRDA_X_MODE_DIV 0x28
#define USP_SM_CFG 0x2C
#define USP_TX_DMA_IO_CTRL 0x100
#define USP_TX_DMA_IO_LEN 0x104
#define USP_TX_FIFO_CTRL 0x108
#define USP_TX_FIFO_LEVEL_CHK 0x10C
#define USP_TX_FIFO_OP 0x110
#define USP_TX_FIFO_STATUS 0x114
#define USP_TX_FIFO_DATA 0x118
#define USP_RX_DMA_IO_CTRL 0x120
#define USP_RX_DMA_IO_LEN 0x124
#define USP_RX_FIFO_CTRL 0x128
#define USP_RX_FIFO_LEVEL_CHK 0x12C
#define USP_RX_FIFO_OP 0x130
#define USP_RX_FIFO_STATUS 0x134
#define USP_RX_FIFO_DATA 0x138
/* USP MODE register-1 */
#define USP_SYNC_MODE 0x00000001
#define USP_CLOCK_MODE_SLAVE 0x00000002
#define USP_LOOP_BACK_EN 0x00000004
#define USP_HPSIR_EN 0x00000008
#define USP_ENDIAN_CTRL_LSBF 0x00000010
#define USP_EN 0x00000020
#define USP_RXD_ACT_EDGE_FALLING 0x00000040
#define USP_TXD_ACT_EDGE_FALLING 0x00000080
#define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100
#define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200
#define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400
#define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800
#define USP_SCLK_PIN_MODE_IO 0x00001000
#define USP_RFS_PIN_MODE_IO 0x00002000
#define USP_TFS_PIN_MODE_IO 0x00004000
#define USP_RXD_PIN_MODE_IO 0x00008000
#define USP_TXD_PIN_MODE_IO 0x00010000
#define USP_SCLK_IO_MODE_INPUT 0x00020000
#define USP_RFS_IO_MODE_INPUT 0x00040000
#define USP_TFS_IO_MODE_INPUT 0x00080000
#define USP_RXD_IO_MODE_INPUT 0x00100000
#define USP_TXD_IO_MODE_INPUT 0x00200000
#define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000
#define USP_IRDA_WIDTH_DIV_OFFSET 0
#define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000
#define USP_TX_UFLOW_REPEAT_ZERO 0x80000000
#define USP_TX_ENDIAN_MODE 0x00000020
#define USP_RX_ENDIAN_MODE 0x00000020
/* USP Mode Register-2 */
#define USP_RXD_DELAY_LEN_MASK 0x000000FF
#define USP_RXD_DELAY_LEN_OFFSET 0
#define USP_TXD_DELAY_LEN_MASK 0x0000FF00
#define USP_TXD_DELAY_LEN_OFFSET 8
#define USP_ENA_CTRL_MODE 0x00010000
#define USP_FRAME_CTRL_MODE 0x00020000
#define USP_TFS_SOURCE_MODE 0x00040000
#define USP_TFS_MS_MODE 0x00080000
#define USP_CLK_DIVISOR_MASK 0x7FE00000
#define USP_CLK_DIVISOR_OFFSET 21
#define USP_TFS_CLK_SLAVE_MODE (1<<20)
#define USP_RFS_CLK_SLAVE_MODE (1<<19)
#define USP_IRDA_DATA_WIDTH 0x80000000
/* USP Transmit Frame Control Register */
#define USP_TXC_DATA_LEN_MASK 0x000000FF
#define USP_TXC_DATA_LEN_OFFSET 0
#define USP_TXC_SYNC_LEN_MASK 0x0000FF00
#define USP_TXC_SYNC_LEN_OFFSET 8
#define USP_TXC_FRAME_LEN_MASK 0x00FF0000
#define USP_TXC_FRAME_LEN_OFFSET 16
#define USP_TXC_SHIFTER_LEN_MASK 0x1F000000
#define USP_TXC_SHIFTER_LEN_OFFSET 24
#define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000
#define USP_TXC_CLK_DIVISOR_MASK 0xC0000000
#define USP_TXC_CLK_DIVISOR_OFFSET 30
/* USP Receive Frame Control Register */
#define USP_RXC_DATA_LEN_MASK 0x000000FF
#define USP_RXC_DATA_LEN_OFFSET 0
#define USP_RXC_FRAME_LEN_MASK 0x0000FF00
#define USP_RXC_FRAME_LEN_OFFSET 8
#define USP_RXC_SHIFTER_LEN_MASK 0x001F0000
#define USP_RXC_SHIFTER_LEN_OFFSET 16
#define USP_START_EDGE_MODE 0x00800000
#define USP_I2S_SYNC_CHG 0x00200000
#define USP_RXC_CLK_DIVISOR_MASK 0x0F000000
#define USP_RXC_CLK_DIVISOR_OFFSET 24
#define USP_SINGLE_SYNC_MODE 0x00400000
/* Tx - RX Enable Register */
#define USP_RX_ENA 0x00000001
#define USP_TX_ENA 0x00000002
/* USP Interrupt Enable and status Register */
#define USP_RX_DONE_INT 0x00000001
#define USP_TX_DONE_INT 0x00000002
#define USP_RX_OFLOW_INT 0x00000004
#define USP_TX_UFLOW_INT 0x00000008
#define USP_RX_IO_DMA_INT 0x00000010
#define USP_TX_IO_DMA_INT 0x00000020
#define USP_RXFIFO_FULL_INT 0x00000040
#define USP_TXFIFO_EMPTY_INT 0x00000080
#define USP_RXFIFO_THD_INT 0x00000100
#define USP_TXFIFO_THD_INT 0x00000200
#define USP_UART_FRM_ERR_INT 0x00000400
#define USP_RX_TIMEOUT_INT 0x00000800
#define USP_TX_ALLOUT_INT 0x00001000
#define USP_RXD_BREAK_INT 0x00008000
/* All possible TX interruots */
#define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\
USP_TX_IO_DMA_INT|\
USP_TXFIFO_EMPTY_INT|\
USP_TXFIFO_THD_INT)
/* All possible RX interruots */
#define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\
USP_RX_IO_DMA_INT|\
USP_RXFIFO_FULL_INT|\
USP_RXFIFO_THD_INT|\
USP_RX_TIMEOUT_INT)
#define USP_INT_ALL 0x1FFF
/* USP Pin I/O Data Register */
#define USP_RFS_PIN_VALUE_MASK 0x00000001
#define USP_TFS_PIN_VALUE_MASK 0x00000002
#define USP_RXD_PIN_VALUE_MASK 0x00000004
#define USP_TXD_PIN_VALUE_MASK 0x00000008
#define USP_SCLK_PIN_VALUE_MASK 0x00000010
/* USP RISC/DSP Mode Register */
#define USP_RISC_DSP_SEL 0x00000001
/* USP ASYNC PARAMETER Register*/
#define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF
#define USP_ASYNC_TIMEOUT_OFFSET 0
#define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \
<<USP_ASYNC_TIMEOUT_OFFSET)
#define USP_ASYNC_DIV2_MASK 0x003F0000
#define USP_ASYNC_DIV2_OFFSET 16
/* USP TX DMA I/O MODE Register */
#define USP_TX_MODE_IO 0x00000001
/* USP TX DMA I/O Length Register */
#define USP_TX_DATA_LEN_MASK 0xFFFFFFFF
#define USP_TX_DATA_LEN_OFFSET 0
/* USP TX FIFO Control Register */
#define USP_TX_FIFO_WIDTH_MASK 0x00000003
#define USP_TX_FIFO_WIDTH_OFFSET 0
#define USP_TX_FIFO_THD_MASK 0x000001FC
#define USP_TX_FIFO_THD_OFFSET 2
/* USP TX FIFO Level Check Register */
#define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F
#define USP_TX_FIFO_SC_OFFSET 0
#define USP_TX_FIFO_LC_OFFSET 10
#define USP_TX_FIFO_HC_OFFSET 20
#define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_SC_OFFSET)
#define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_LC_OFFSET)
#define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_HC_OFFSET)
/* USP TX FIFO Operation Register */
#define USP_TX_FIFO_RESET 0x00000001
#define USP_TX_FIFO_START 0x00000002
/* USP TX FIFO Status Register */
#define USP_TX_FIFO_LEVEL_MASK 0x0000007F
#define USP_TX_FIFO_LEVEL_OFFSET 0
#define USP_TX_FIFO_FULL 0x00000080
#define USP_TX_FIFO_EMPTY 0x00000100
/* USP TX FIFO Data Register */
#define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF
#define USP_TX_FIFO_DATA_OFFSET 0
/* USP RX DMA I/O MODE Register */
#define USP_RX_MODE_IO 0x00000001
#define USP_RX_DMA_FLUSH 0x00000004
/* USP RX DMA I/O Length Register */
#define USP_RX_DATA_LEN_MASK 0xFFFFFFFF
#define USP_RX_DATA_LEN_OFFSET 0
/* USP RX FIFO Control Register */
#define USP_RX_FIFO_WIDTH_MASK 0x00000003
#define USP_RX_FIFO_WIDTH_OFFSET 0
#define USP_RX_FIFO_THD_MASK 0x000001FC
#define USP_RX_FIFO_THD_OFFSET 2
/* USP RX FIFO Level Check Register */
#define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F
#define USP_RX_FIFO_SC_OFFSET 0
#define USP_RX_FIFO_LC_OFFSET 10
#define USP_RX_FIFO_HC_OFFSET 20
#define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_SC_OFFSET)
#define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_LC_OFFSET)
#define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_HC_OFFSET)
/* USP RX FIFO Operation Register */
#define USP_RX_FIFO_RESET 0x00000001
#define USP_RX_FIFO_START 0x00000002
/* USP RX FIFO Status Register */
#define USP_RX_FIFO_LEVEL_MASK 0x0000007F
#define USP_RX_FIFO_LEVEL_OFFSET 0
#define USP_RX_FIFO_FULL 0x00000080
#define USP_RX_FIFO_EMPTY 0x00000100
/* USP RX FIFO Data Register */
#define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF
#define USP_RX_FIFO_DATA_OFFSET 0
/*
* When rx thd irq occur, sender just disable tx empty irq,
* Remaining data in tx fifo wil also be sent out.
*/
#define USP_FIFO_SIZE 128
#define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
#define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
/* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */
#define USP_FIFO_WIDTH_BYTE 0x00
#define USP_FIFO_WIDTH_WORD 0x01
#define USP_FIFO_WIDTH_DWORD 0x02
#define USP_ASYNC_DIV2 16
#define USP_PLUGOUT_RETRY_CNT 2
#define USP_TX_RX_FIFO_WIDTH_DWORD 2
#define SIRF_USP_DIV_MCLK 0
#define SIRF_USP_I2S_TFS_SYNC 0
#define SIRF_USP_I2S_RFS_SYNC 1
#endif
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