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Commit 62c79bb3 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM 64-bit DT updates from Olof Johansson:
 "This is the first release where we split up the 64-bit contributions a
  bit more, and in particular we are having a separate DT branch for
  them.

  Contents:

   - New devices added to Broadcom NorthStar2
   - Misc fixes for Exynos7 boards
   - QCOM updates for MSM8916
   - Rockchip tweaks for rk3368 SoC and eval board
   - A series of fixes for APM X-Gene v1 and v2
   - Renesas R8A7795 CPU/PSCI additions
   - Marvell Berlin4CT PSCI, cpuidle, watchdog portions
   - Freescale LS1043a SoC and dev board support

  + some treewide or other misc changes"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
  dts/ls2080a: Update DTSI to add support of SP805 WDT
  Documentation: DT: Add entry for ARM SP805-WDT
  arm64: dts: X-Gene v2: I2C1 clock is always on
  arm64: dts: X-Gene v1: I2C0 clock is always on
  arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms
  arm64: dts: hikey: add label properties to UARTs
  arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI
  arm64: dts: apq8016-sbc: enable UART0 on LS connector
  arm64: dts: juno: Add idle-states to device tree
  arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC
  arm64: dts: add LS1043a-RDB board support
  arm64: dts: add Freescale LS1043a SoC support
  Documentation: DT: Add entry for Freescale LS1043a-RDB board
  arm64: dts: uniphier: add PH1-LD10 SoC/board support
  arm64: renesas: r8a7795: fix SATA clock assignment
  arm64: dts: salvator-x: Enable SATA controller
  arm64: dts: r8a7795: Add SATA controller node
  arm64: renesas: r8a7795: add internal delay for i2c IPs
  arm64: renesas: salvator-x: Add board part number to DT bindings
  arm64: dts: r8a7795: Add pmu device nodes
  ...
parents 6d1c2448 d07822a7
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Documentation/devicetree/bindings/arm/fsl.txt
View file @ 62c79bb3
......@@ -131,6 +131,10 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
LS1043A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
......
Documentation/devicetree/bindings/arm/rockchip.txt
View file @ 62c79bb3
......@@ -87,6 +87,10 @@ Rockchip platforms device tree bindings
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
- Rockchip RK3368 evb:
Required root node properties:
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
- Rockchip R88 board:
Required root node properties:
- compatible = "rockchip,r88", "rockchip,rk3368";
......
Documentation/devicetree/bindings/arm/shmobile.txt
View file @ 62c79bb3
......@@ -27,6 +27,8 @@ SoCs:
compatible = "renesas,r8a7793"
- R-Car E2 (R8A77940)
compatible = "renesas,r8a7794"
- R-Car H3 (R8A77950)
compatible = "renesas,r8a7795"
Boards:
......@@ -57,5 +59,7 @@ Boards:
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
compatible = "renesas,porter", "renesas,r8a7791"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
Documentation/devicetree/bindings/watchdog/sp805-wdt.txt 0 → 100644
View file @ 62c79bb3
* ARM SP805 Watchdog Timer (WDT) Controller
SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
can be used to identify the peripheral type, vendor, and revision.
This value can be used for driver matching.
As SP805 WDT is a primecell IP, it follows the base bindings specified in
'arm/primecell.txt'
Required properties:
- compatible : Should be "arm,sp805-wdt", "arm,primecell"
- reg : Base address and size of the watchdog timer registers.
- clocks : From common clock binding.
First clock is PCLK and the second is WDOGCLK.
WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency.
- clock-names : From common clock binding.
Shall be "apb_pclk" for first clock and "wdog_clk" for the
second one.
Optional properties:
- interrupts : Should specify WDT interrupt number.
Examples:
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
MAINTAINERS
View file @ 62c79bb3
......@@ -1435,6 +1435,15 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/RENESAS ARM64 ARCHITECTURE
M: Simon Horman <horms@verge.net.au>
M: Magnus Damm <magnus.damm@gmail.com>
L: linux-sh@vger.kernel.org
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
S: Supported
F: arch/arm64/boot/dts/renesas/
ARM/RISCPC ARCHITECTURE
M: Russell King <linux@arm.linux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......@@ -1663,6 +1672,7 @@ F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
F: arch/arm64/boot/dts/socionext/
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/pinctrl/uniphier/
F: drivers/tty/serial/8250/8250_uniphier.c
......
arch/arm64/Kconfig.platforms
View file @ 62c79bb3
......@@ -67,6 +67,23 @@ config ARCH_SEATTLE
help
This enables support for AMD Seattle SOC Family
config ARCH_SHMOBILE
bool
config ARCH_RENESAS
bool "Renesas SoC Platforms"
select ARCH_SHMOBILE
select PINCTRL
select PM_GENERIC_DOMAINS if PM
help
This enables support for the ARMv8 based Renesas SoCs.
config ARCH_R8A7795
bool "Renesas R-Car H3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car H3 SoC.
config ARCH_STRATIX10
bool "Altera's Stratix 10 SoCFPGA Family"
help
......
arch/arm64/boot/dts/Makefile
View file @ 62c79bb3
......@@ -10,7 +10,9 @@ dts-dirs += hisilicon
dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += renesas
dts-dirs += rockchip
dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
......
arch/arm64/boot/dts/apm/apm-merlin.dts
View file @ 62c79bb3
......@@ -70,3 +70,15 @@ &sgenet0 {
&xgenet1 {
status = "ok";
};
&mmc0 {
status = "ok";
};
&i2c4 {
rtc68: rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
status = "ok";
};
};
arch/arm64/boot/dts/apm/apm-mustang.dts
View file @ 62c79bb3
......@@ -74,3 +74,7 @@ &sgenet1 {
&xgenet {
status = "ok";
};
&mmc0 {
status = "ok";
};
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View file @ 62c79bb3
This diff is collapsed.
arch/arm64/boot/dts/apm/apm-storm.dtsi
View file @ 62c79bb3
......@@ -25,6 +25,7 @@ cpu@000 {
reg = <0x0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
};
cpu@001 {
device_type = "cpu";
......@@ -32,6 +33,7 @@ cpu@001 {
reg = <0x0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
};
cpu@100 {
device_type = "cpu";
......@@ -39,6 +41,7 @@ cpu@100 {
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
};
cpu@101 {
device_type = "cpu";
......@@ -46,6 +49,7 @@ cpu@101 {
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
};
cpu@200 {
device_type = "cpu";
......@@ -53,6 +57,7 @@ cpu@200 {
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
};
cpu@201 {
device_type = "cpu";
......@@ -60,6 +65,7 @@ cpu@201 {
reg = <0x0 0x201>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
};
cpu@300 {
device_type = "cpu";
......@@ -67,6 +73,7 @@ cpu@300 {
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
};
cpu@301 {
device_type = "cpu";
......@@ -74,6 +81,19 @@ cpu@301 {
reg = <0x0 0x301>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
};
};
......@@ -150,6 +170,35 @@ socplldiv2: socplldiv2 {
clock-output-names = "socplldiv2";
};
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
divider-width = <0x5>;
divider-shift = <0x0>;
clock-output-names = "ahbclk";
};
sdioclk: sdioclk@1f2ac000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
csr-offset = <0x0>;
csr-mask = <0x2>;
enable-offset = <0x8>;
enable-mask = <0x2>;
divider-offset = <0x178>;
divider-width = <0x8>;
divider-shift = <0x0>;
clock-output-names = "sdioclk";
};
qmlclk: qmlclk {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
......@@ -686,6 +735,50 @@ serial3: serial@1c023000 {
interrupts = <0x0 0x4f 0x4>;
};
mmc0: mmc@1c000000 {
compatible = "arasan,sdhci-4.9a";
reg = <0x0 0x1c000000 0x0 0x100>;
interrupts = <0x0 0x49 0x4>;
dma-coherent;
no-1-8-v;
clock-names = "clk_xin", "clk_ahb";
clocks = <&sdioclk 0>, <&ahbclk 0>;
};
gfcgpio: gpio0@1701c000 {
compatible = "apm,xgene-gpio";
reg = <0x0 0x1701c000 0x0 0x40>;
gpio-controller;
#gpio-cells = <2>;
};
dwgpio: gpio@1c024000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x1c024000 0x0 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <32>;
reg = <0>;
};
};
i2c0: i2c@10512000 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10512000 0x0 0x1000>;
interrupts = <0 0x44 0x4>;
#clock-cells = <1>;
clocks = <&ahbclk 0>;
bus_num = <0>;
};
phy1: phy@1f21a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
......@@ -760,7 +853,26 @@ sata3: sata@1a800000 {
phy-names = "sata-phy";
};
sbgpio: sbgpio@17001000{
/* Do not change dwusb name, coded for backward compatibility */
usb0: dwusb@19000000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x19000000 0x0 0x100000>;
interrupts = <0x0 0x89 0x4>;
dma-coherent;
dr_mode = "host";
};
usb1: dwusb@19800000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x19800000 0x0 0x100000>;
interrupts = <0x0 0x8a 0x4>;
dma-coherent;
dr_mode = "host";
};
sbgpio: gpio@17001000{
compatible = "apm,xgene-gpio-sb";
reg = <0x0 0x17001000 0x0 0x400>;
#gpio-cells = <2>;
......
arch/arm64/boot/dts/arm/juno-r1.dts
View file @ 62c79bb3
......@@ -60,6 +60,28 @@ core3 {
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
......@@ -67,6 +89,7 @@ A57_0: cpu@0 {
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_1: cpu@1 {
......@@ -76,6 +99,7 @@ A57_1: cpu@1 {
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
......@@ -85,6 +109,7 @@ A53_0: cpu@100 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
......@@ -94,6 +119,7 @@ A53_1: cpu@101 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
......@@ -103,6 +129,7 @@ A53_2: cpu@102 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
......@@ -112,6 +139,7 @@ A53_3: cpu@103 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_L2: l2-cache0 {
......
arch/arm64/boot/dts/arm/juno.dts
View file @ 62c79bb3
......@@ -60,6 +60,28 @@ core3 {
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
......@@ -67,6 +89,7 @@ A57_0: cpu@0 {
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_1: cpu@1 {
......@@ -76,6 +99,7 @@ A57_1: cpu@1 {
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
......@@ -85,6 +109,7 @@ A53_0: cpu@100 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
......@@ -94,6 +119,7 @@ A53_1: cpu@101 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
......@@ -103,6 +129,7 @@ A53_2: cpu@102 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
......@@ -112,6 +139,7 @@ A53_3: cpu@103 {
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_L2: l2-cache0 {
......
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View file @ 62c79bb3
......@@ -50,10 +50,28 @@ memory {
device_type = "memory";
reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
};
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&uart3 {
status = "ok";
};
soc: soc {
uart3: serial@66130000 {
status = "ok";
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
#address-cells = <1>;
#size-cells = <1>;
};
};
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file @ 62c79bb3
......@@ -31,6 +31,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>
/memreserve/ 0x84b00000 0x00000008;
......@@ -44,36 +45,44 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
A57_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 0>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
};
cpu@1 {
A57_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 1>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
};
cpu@2 {
A57_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 2>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
};
cpu@3 {
A57_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 3>;
enable-method = "spin-table";
cpu-release-addr = <0 0x84b00000>;
next-level-cache = <&CLUSTER0_L2>;
};
CLUSTER0_L2: l2-cache@000 {
compatible = "cache";
};
};
......@@ -89,12 +98,154 @@ IRQ_TYPE_EDGE_RISING)>,
IRQ_TYPE_EDGE_RISING)>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A57_0>,
<&A57_1>,
<&A57_2>,
<&A57_3>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
iprocmed: iprocmed {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
iprocslow: iprocslow {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
smmu: mmu@64000000 {
compatible = "arm,mmu-500";
reg = <0x64000000 0x40000>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
mmu-masters;
};
lcpll_ddr: lcpll_ddr@6501d058 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ddr";
reg = <0x6501d058 0x20>,
<0x6501c020 0x4>,
<0x6501d04c 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
"ddr", "ddr_ch2_unused",
"ddr_ch3_unused", "ddr_ch4_unused",
"ddr_ch5_unused";
};
lcpll_ports: lcpll_ports@6501d078 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ports";
reg = <0x6501d078 0x20>,
<0x6501c020 0x4>,
<0x6501d054 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ports", "wan", "rgmii",
"ports_ch2_unused",
"ports_ch3_unused",
"ports_ch4_unused",
"ports_ch5_unused";
};
genpll_scr: genpll_scr@6501d098 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-scr";
reg = <0x6501d098 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_scr", "scr", "fs",
"audio_ref", "scr_ch3_unused",
"scr_ch4_unused", "scr_ch5_unused";
};
genpll_sw: genpll_sw@6501d0c4 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-sw";
reg = <0x6501d0c4 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_sw", "rpe", "250", "nic",
"chimp", "port", "sdio";
};
crmu: crmu@65024000 {
compatible = "syscon";
reg = <0x65024000 0x100>;
};
reboot@65024000 {
compatible ="syscon-reboot";
regmap = <&crmu>;
offset = <0x90>;
mask = <0xfffffffd>;
};
gic: interrupt-controller@65210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
......@@ -105,14 +256,53 @@ gic: interrupt-controller@65210000 {
<0x65260000 0x1000>;
};
i2c0: i2c@66080000 {
compatible = "brcm,iproc-i2c";
reg = <0x66080000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@660b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x660b0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart3: serial@66130000 {
compatible = "snps,dw-apb-uart";
reg = <0x66130000 0x100>;
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <23961600>;
clocks = <&osc>;
status = "disabled";
};
hwrng: hwrng@66220000 {
compatible = "brcm,iproc-rng200";
reg = <0x66220000 0x28>;
};
nand: nand@66460000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x66460000 0x600>,
<0x67015408 0x600>,
<0x66460f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
};
};
};
arch/arm64/boot/dts/exynos/exynos7-espresso.dts
View file @ 62c79bb3
......@@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos7.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
......@@ -52,11 +53,288 @@ &adc {
status = "okay";
};
&hsi2c_4 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <200000>;
status = "okay";
s2mps15_pmic@66 {
compatible = "samsung,s2mps15-pmic";
reg = <0x66>;
interrupts = <2 IRQ_TYPE_NONE>;
interrupt-parent = <&gpa0>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq>;
wakeup-source;
s2mps15_osc: clocks {
compatible = "samsung,s2mps13-clk";
#clock-cells = <1>;
clock-output-names = "s2mps13_ap", "s2mps13_cp",
"s2mps13_bt";
};
regulators {
ldo1_reg: LDO1 {
regulator-name = "vdd_ldo1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo2_reg: LDO2 {
regulator-name = "vqmmc-sdcard";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo3_reg: LDO3 {
regulator-name = "vdd_ldo3";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <125>;
};
ldo4_reg: LDO4 {
regulator-name = "vdd_ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1110000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo5_reg: LDO5 {
regulator-name = "vdd_ldo5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo6_reg: LDO6 {
regulator-name = "vdd_ldo6";
regulator-min-microvolt = <2250000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <125>;
};
ldo7_reg: LDO7 {
regulator-name = "vdd_ldo7";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1150000>;
regulator-enable-ramp-delay = <125>;
};
ldo8_reg: LDO8 {
regulator-name = "vdd_ldo8";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1000000>;
regulator-enable-ramp-delay = <125>;
};
ldo9_reg: LDO9 {
regulator-name = "vdd_ldo9";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1000000>;
regulator-enable-ramp-delay = <125>;
};
ldo10_reg: LDO10 {
regulator-name = "vdd_ldo10";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1000000>;
regulator-enable-ramp-delay = <125>;
};
ldo11_reg: LDO11 {
regulator-name = "vdd_ldo11";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo12_reg: LDO12 {
regulator-name = "vdd_ldo12";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-enable-ramp-delay = <125>;
};
ldo13_reg: LDO13 {
regulator-name = "vdd_ldo13";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-enable-ramp-delay = <125>;
};
ldo14_reg: LDO14 {
regulator-name = "vdd_ldo14";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-enable-ramp-delay = <125>;
};
ldo17_reg: LDO17 {
regulator-name = "vmmc-sdcard";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-enable-ramp-delay = <125>;
};
ldo18_reg: LDO18 {
regulator-name = "vdd_ldo18";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2275000>;
regulator-enable-ramp-delay = <125>;
};
ldo19_reg: LDO19 {
regulator-name = "vdd_ldo19";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-enable-ramp-delay = <125>;
};
ldo21_reg: LDO21 {
regulator-name = "vdd_ldo21";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-enable-ramp-delay = <125>;
};
ldo23_reg: LDO23 {
regulator-name = "vdd_ldo23";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2275000>;
regulator-enable-ramp-delay = <125>;
};
ldo25_reg: LDO25 {
regulator-name = "vdd_ldo25";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-enable-ramp-delay = <125>;
};
ldo26_reg: LDO26 {
regulator-name = "vdd_ldo26";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1470000>;
regulator-enable-ramp-delay = <125>;
};
ldo27_reg: LDO27 {
regulator-name = "vdd_ldo27";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2275000>;
regulator-enable-ramp-delay = <125>;
};
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
buck2_reg: BUCK2 {
regulator-name = "vdd_atlas";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <250>;
};
buck4_reg: BUCK4 {
regulator-name = "vdd_int";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <250>;
};
buck5_reg: BUCK5 {
regulator-name = "vdd_buck5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
buck6_reg: BUCK6 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <12500>;
regulator-enable-ramp-delay = <250>;
};
buck7_reg: BUCK7 {
regulator-name = "vdd_buck7";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
buck8_reg: BUCK8 {
regulator-name = "vdd_buck8";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
buck9_reg: BUCK9 {
regulator-name = "vdd_buck9";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
regulator-always-on;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
buck10_reg: BUCK10 {
regulator-name = "vdd_buck10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-ramp-delay = <25000>;
regulator-enable-ramp-delay = <250>;
};
};
};
};
&pinctrl_alive {
pmic_irq: pmic-irq {
samsung,pins = "gpa0-2";
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
};
&mmc_0 {
status = "okay";
num-slots = <1>;
broken-cd;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
card-detect-delay = <200>;
clock-frequency = <800000000>;
......@@ -80,5 +358,7 @@ &mmc_2 {
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
vmmc-supply = <&ldo17_reg>;
vqmmc-supply = <&ldo2_reg>;
disable-wp;
};
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file @ 62c79bb3
......@@ -454,6 +454,13 @@ pmu_system_controller: system-controller@105c0000 {
reg = <0x105c0000 0x5000>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&pmu_system_controller>;
offset = <0x0400>;
mask = <0x1>;
};
rtc: rtc@10590000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10590000 0x100>;
......
arch/arm64/boot/dts/freescale/Makefile
View file @ 62c79bb3
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts 0 → 100644
View file @ 62c79bb3
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
};
&i2c0 {
status = "okay";
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
adt7461a@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
eeprom@52 {
compatible = "at24,24c512";
reg = <0x52>;
};
eeprom@53 {
compatible = "at24,24c512";
reg = <0x53>;
};
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
nor@0,0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
cpld: board-control@2,0 {
compatible = "fsl,ls1043ardb-cpld";
reg = <0x2 0x0 0x0000100>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 0 → 100644
View file @ 62c79bb3
This diff is collapsed.
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ 62c79bb3
......@@ -153,6 +153,18 @@ its: gic-its@6020000 {
};
};
rstcr: syscon@1e60000 {
compatible = "fsl,ls2080a-rstcr", "syscon";
reg = <0x0 0x1e60000 0x0 0x4>;
};
reboot {
compatible ="syscon-reboot";
regmap = <&rstcr>;
offset = <0x0>;
mask = <0x2>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
......@@ -193,6 +205,62 @@ serial1: serial@21c0600 {
interrupts = <0 32 0x4>; /* Level high type */
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
......
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View file @ 62c79bb3
......@@ -32,3 +32,10 @@ memory@0 {
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&uart2 {
label = "LS-UART0";
};
&uart3 {
label = "LS-UART1";
};
arch/arm64/boot/dts/marvell/berlin4ct.dtsi
View file @ 62c79bb3
......@@ -55,7 +55,7 @@ aliases {
};
psci {
compatible = "arm,psci-0.2";
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
......@@ -68,6 +68,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu1: cpu@1 {
......@@ -75,6 +76,7 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu2: cpu@2 {
......@@ -82,6 +84,7 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu3: cpu@3 {
......@@ -89,6 +92,19 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <75>;
exit-latency-us = <155>;
min-residency-us = <1000>;
};
};
};
......@@ -225,6 +241,16 @@ aic: interrupt-controller@3800 {
};
};
soc_pinctrl: pin-controller@ea8000 {
compatible = "marvell,berlin4ct-soc-pinctrl";
reg = <0xea8000 0x14>;
};
avio_pinctrl: pin-controller@ea8400 {
compatible = "marvell,berlin4ct-avio-pinctrl";
reg = <0xea8400 0x8>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -241,6 +267,29 @@ sic: interrupt-controller@1000 {
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
wdt0: watchdog@3000 {
compatible = "snps,dw-wdt";
reg = <0x3000 0x100>;
clocks = <&osc>;
interrupts = <0>;
};
wdt1: watchdog@4000 {
compatible = "snps,dw-wdt";
reg = <0x4000 0x100>;
clocks = <&osc>;
interrupts = <1>;
status = "disabled";
};
wdt2: watchdog@5000 {
compatible = "snps,dw-wdt";
reg = <0x5000 0x100>;
clocks = <&osc>;
interrupts = <2>;
status = "disabled";
};
sm_gpio0: gpio@8000 {
compatible = "snps,dw-apb-gpio";
reg = <0x8000 0x400>;
......@@ -278,6 +327,18 @@ uart0: uart@d000 {
clocks = <&osc>;
reg-shift = <2>;
status = "disabled";
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
};
};
system_pinctrl: pin-controller@fe2200 {
compatible = "marvell,berlin4ct-system-pinctrl";
reg = <0xfe2200 0xc>;
uart0_pmux: uart0-pmux {
groups = "SM_URT0_TXD", "SM_URT0_RXD";
function = "uart0";
};
};
};
......
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View file @ 62c79bb3
......@@ -102,6 +102,13 @@ &mmc1 {
};
&pio {
disp_pwm0_pins: disp_pwm0_pins {
pins1 {
pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
output-low;
};
};
mmc0_pins_default: mmc0default {
pins_cmd_dat {
pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
......@@ -200,6 +207,12 @@ pins_clk {
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&disp_pwm0_pins>;
status = "okay";
};
&pwrap {
pmic: mt6397 {
compatible = "mediatek,mt6397";
......
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file @ 62c79bb3
......@@ -96,7 +96,7 @@ CPU_SLEEP_0: cpu-sleep-0 {
};
psci {
compatible = "arm,psci";
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
......@@ -248,6 +248,15 @@ watchdog: watchdog@10007000 {
reg = <0 0x10007000 0 0x100>;
};
timer: timer@10008000 {
compatible = "mediatek,mt8173-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CLK_13M>,
<&topckgen CLK_TOP_RTC_SEL>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8173-pwrap";
reg = <0 0x1000d000 0 0x1000>;
......@@ -558,6 +567,28 @@ mmsys: clock-controller@14000000 {
#clock-cells = <1>;
};
pwm0: pwm@1401e000 {
compatible = "mediatek,mt8173-disp-pwm",
"mediatek,mt6595-disp-pwm";
reg = <0 0x1401e000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
<&mmsys CLK_MM_DISP_PWM0MM>;
clock-names = "main", "mm";
status = "disabled";
};
pwm1: pwm@1401f000 {
compatible = "mediatek,mt8173-disp-pwm",
"mediatek,mt6595-disp-pwm";
reg = <0 0x1401f000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&mmsys CLK_MM_DISP_PWM126M>,
<&mmsys CLK_MM_DISP_PWM1MM>;
clock-names = "main", "mm";
status = "disabled";
};
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8173-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
......
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ 62c79bb3
......@@ -20,6 +20,10 @@ / {
aliases {
serial0 = &blsp1_uart2;
serial1 = &blsp1_uart1;
usid0 = &pm8916_0;
i2c0 = &blsp_i2c2;
i2c1 = &blsp_i2c6;
i2c3 = &blsp_i2c4;
};
chosen {
......@@ -27,7 +31,16 @@ chosen {
};
soc {
serial@78af000 {
label = "LS-UART0";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
};
serial@78b0000 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
......@@ -36,26 +49,31 @@ serial@78b0000 {
i2c@78b6000 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
i2c@78b8000 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
};
i2c@78ba000 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
spi@78b7000 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
spi@78b9000 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
......
arch/arm64/boot/dts/qcom/msm8916-mtp.dts
View file @ 62c79bb3
......@@ -17,6 +17,6 @@
/ {
model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1",
"qcom,msm8916", "qcom,mtp";
};
arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
View file @ 62c79bb3
......@@ -17,6 +17,7 @@
/ {
aliases {
serial0 = &blsp1_uart2;
usid0 = &pm8916_0;
};
chosen {
......
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
View file @ 62c79bb3
......@@ -16,10 +16,13 @@ &msmgpio {
blsp1_uart1_default: blsp1_uart1_default {
pinmux {
function = "blsp_uart1";
pins = "gpio0", "gpio1";
// TX, RX, CTS_N, RTS_N
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1";
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <16>;
bias-disable;
};
......@@ -28,10 +31,12 @@ pinconf {
blsp1_uart1_sleep: blsp1_uart1_sleep {
pinmux {
function = "gpio";
pins = "gpio0", "gpio1";
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
pinconf {
pins = "gpio0", "gpio1";
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <2>;
bias-pull-down;
};
......@@ -272,7 +277,7 @@ pinmux {
};
pinconf {
pins = "gpio6", "gpio7";
drive-strength = <2>;
drive-strength = <16>;
bias-disable = <0>;
};
};
......@@ -296,7 +301,7 @@ pinmux {
};
pinconf {
pins = "gpio14", "gpio15";
drive-strength = <2>;
drive-strength = <16>;
bias-disable = <0>;
};
};
......@@ -320,7 +325,7 @@ pinmux {
};
pinconf {
pins = "gpio22", "gpio23";
drive-strength = <2>;
drive-strength = <16>;
bias-disable = <0>;
};
};
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 62c79bb3
......@@ -37,6 +37,22 @@ memory {
reg = <0 0 0 0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserve_aligned@86000000 {
reg = <0x0 0x86000000 0x0 0x0300000>;
no-map;
};
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x0100000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
......@@ -74,6 +90,29 @@ timer {
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -103,21 +142,46 @@ gcc: qcom,gcc@1800000 {
reg = <0x1800000 0x80000>;
};
tcsr_mutex_regs: syscon@1905000 {
compatible = "syscon";
reg = <0x1905000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
rpm_msg_ram: memory@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x60000 0x8000>;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 1>, <&blsp_dma 0>;
dma-names = "rx", "tx";
status = "disabled";
};
apcs: syscon@b011000 {
compatible = "syscon";
reg = <0x0b011000 0x1000>;
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 3>, <&blsp_dma 2>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -438,6 +502,49 @@ rng@22000 {
clock-names = "core";
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-msm8916";
qcom,smd-channels = "rpm_requests";
pm8916-regulators {
compatible = "qcom,rpm-pm8916-regulators";
pm8916_s1: s1 {};
pm8916_s2: s2 {};
pm8916_s3: s3 {};
pm8916_s4: s4 {};
pm8916_l1: l1 {};
pm8916_l2: l2 {};
pm8916_l3: l3 {};
pm8916_l4: l4 {};
pm8916_l5: l5 {};
pm8916_l6: l6 {};
pm8916_l7: l7 {};
pm8916_l8: l8 {};
pm8916_l9: l9 {};
pm8916_l10: l10 {};
pm8916_l11: l11 {};
pm8916_l12: l12 {};
pm8916_l13: l13 {};
pm8916_l14: l14 {};
pm8916_l15: l15 {};
pm8916_l16: l16 {};
pm8916_l17: l17 {};
pm8916_l18: l18 {};
};
};
};
};
};
#include "msm8916-pins.dtsi"
arch/arm64/boot/dts/qcom/pm8916.dtsi
View file @ 62c79bb3
......@@ -4,8 +4,8 @@
&spmi_bus {
usid0: pm8916@0 {
compatible = "qcom,spmi-pmic";
pm8916_0: pm8916@0 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -90,7 +90,7 @@ ref_vdd {
};
};
usid1: pm8916@1 {
pm8916_1: pm8916@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
......
arch/arm64/boot/dts/renesas/Makefile 0 → 100644
View file @ 62c79bb3
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 0 → 100644
View file @ 62c79bb3
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/*
* SSI-AK4613
*
* This command is required when Playback/Capture
*
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
/dts-v1/;
#include "r8a7795.dtsi"
/ {
model = "Renesas Salvator-X board based on r8a7795";
compatible = "renesas,salvator-x", "renesas,r8a7795";
aliases {
serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
x12_clk: x12_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
audio_clkout: audio_clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&pfc {
scif1_pins: scif1 {
renesas,groups = "scif1_data_a", "scif1_ctrl";
renesas,function = "scif1";
};
scif2_pins: scif2 {
renesas,groups = "scif2_data_a";
renesas,function = "scif2";
};
i2c2_pins: i2c2 {
renesas,groups = "i2c2_a";
renesas,function = "i2c2";
};
avb_pins: avb {
renesas,groups = "avb_mdc";
renesas,function = "avb";
};
sound_pins: sound {
renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
renesas,function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout3_a";
renesas,function = "audio_clk";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk_multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <11289600>;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&sata {
status = "okay";
};
&ssi1 {
shared-pin;
};
&audio_clk_a {
clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <900>;
rxdv-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txc-skew-ps = <900>;
txen-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
arch/arm64/boot/dts/renesas/r8a7795.dtsi 0 → 100644
View file @ 62c79bb3
This diff is collapsed.
arch/arm64/boot/dts/rockchip/Makefile
View file @ 62c79bb3
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
always := $(dtb-y)
......
arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts 0 → 100644
View file @ 62c79bb3
/*
* Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3368-evb.dtsi"
/ {
model = "Rockchip RK3368 EVB with ACT8846 pmic";
compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
};
&i2c0 {
clock-frequency = <400000>;
vdd_cpu: syr827@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vdd_gpu: syr828@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
act8846: act8846@5a {
compatible = "active-semi,act8846";
reg = <0x5a>;
status = "okay";
vp1-supply = <&vcc_sys>;
vp2-supply = <&vcc_sys>;
vp3-supply = <&vcc_sys>;
vp4-supply = <&vcc_sys>;
inl1-supply = <&vcc_io>;
inl2-supply = <&vcc_sys>;
inl3-supply = <&vcc_20>;
regulators {
vcc_ddr: REG1 {
regulator-name = "VCC_DDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_io: REG2 {
regulator-name = "VCC_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_log: REG3 {
regulator-name = "VDD_LOG";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vcc_20: REG4 {
regulator-name = "VCC_20";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-always-on;
};
vccio_sd: REG5 {
regulator-name = "VCCIO_SD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd10_lcd: REG6 {
regulator-name = "VDD10_LCD";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vcca_codec: REG7 {
regulator-name = "VCCA_CODEC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcca_tp: REG8 {
regulator-name = "VCCA_TP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccio_pmu: REG9 {
regulator-name = "VCCIO_PMU";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_10: REG10 {
regulator-name = "VDD_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vcc_18: REG11 {
regulator-name = "VCC_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc18_lcd: REG12 {
regulator-name = "VCC18_LCD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
};
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi 0 → 100644
View file @ 62c79bb3
/*
* Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pwm/pwm.h>
#include "rk3368.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
pwm-delay-us = <10000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
};
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
button@0 {
gpio-key,wakeup = <1>;
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <116>;
};
};
/* supplies both host and otg */
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_lan: vcc-lan-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_lan";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac {
phy-supply = <&vcc_lan>;
phy-mode = "rmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 12 0>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
};
&i2c0 {
status = "okay";
};
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable;
drive-strength = <8>;
};
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
};
backlight {
bl_en: bl-en {
rockchip,pins = <0 20 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
emmc {
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
emmc-clk {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
};
emmc-cmd {
rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
emmc_reset: emmc-reset {
rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
keys {
pwr_key: pwr-key {
rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio {
wifi_reg_on: wifi-reg-on {
rockchip,pins = <3 4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_rst: bt-rst {
rockchip,pins = <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};
&wdt {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View file @ 62c79bb3
......@@ -336,6 +336,12 @@ &saradc {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "okay";
};
&uart2 {
status = "okay";
};
......
arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi 0 → 100644
View file @ 62c79bb3
/*
* Device Tree Source for RK3368 SoC thermal
*
* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
* Caesar Wang <wxt@rock-chips.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu_thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
trips {
gpu_alert0: gpu_alert0 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
gpu_crit: gpu_crit {
temperature = <1150000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 62c79bb3
......@@ -45,6 +45,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3368";
......@@ -53,6 +54,7 @@ / {
#size-cells = <2>;
aliases {
ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
......@@ -123,6 +125,8 @@ cpu_l0: cpu@0 {
reg = <0x0 0x0>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_l1: cpu@1 {
......@@ -155,6 +159,8 @@ cpu_b0: cpu@100 {
reg = <0x0 0x100>;
cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
};
cpu_b1: cpu@101 {
......@@ -404,6 +410,27 @@ uart4: serial@ff1c0000 {
status = "disabled";
};
thermal-zones {
#include "rk3368-thermal.dtsi"
};
tsadc: tsadc@ff280000 {
compatible = "rockchip,rk3368-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
gmac: ethernet@ff290000 {
compatible = "rockchip,rk3368-gmac";
reg = <0x0 0xff290000 0x0 0x10000>;
......@@ -471,6 +498,48 @@ i2c2: i2c@ff660000 {
status = "disabled";
};
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
status = "disabled";
};
uart2: serial@ff690000 {
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
reg = <0x0 0xff690000 0x0 0x100>;
......@@ -510,6 +579,12 @@ wdt: watchdog@ff800000 {
status = "disabled";
};
timer@ff810000 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
......@@ -712,6 +787,24 @@ i2c5_xfer: i2c5-xfer {
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
......@@ -762,7 +855,7 @@ sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_cd: sdmcc-cd {
sdmmc_cd: sdmmc-cd {
rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
};
......@@ -829,6 +922,16 @@ spi2_tx: spi2-tx {
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
......
arch/arm64/boot/dts/socionext/Makefile 0 → 100644
View file @ 62c79bb3
dtb-$(CONFIG_ARCH_UNIPHIER) += uniphier-ph1-ld10-ref.dtb
always := $(dtb-y)
clean-files := *.dtb
arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts 0 → 100644
View file @ 62c79bb3
/*
* Device Tree Source for UniPhier PH1-LD10 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "uniphier-ph1-ld10.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD10 Reference Board";
compatible = "socionext,ph1-ld10-ref", "socionext,ph1-ld10";
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
};
&extbus {
ranges = <1 0x00000000 0x42000000 0x02000000>;
};
&support_card {
ranges = <0x00000000 1 0x01f00000 0x00100000>;
};
&ethsc {
interrupts = <0 48 4>;
};
&serial0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi 0 → 100644
View file @ 62c79bb3
/*
* Device Tree Source for UniPhier PH1-LD10 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
compatible = "socionext,ph1-ld10";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu2>;
};
core1 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
};
};
clocks {
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <58820000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf01>,
<1 14 0xf01>,
<1 11 0xf01>,
<1 10 0xf01>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
extbus: extbus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart_clk>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart_clk>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&uart_clk>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&uart_clk>;
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};
i2c1: i2c@58781000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};
i2c2: i2c@58782000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};
i2c3: i2c@58783000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};
i2c4: i2c@58784000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
clocks = <&i2c_clk>;
clock-frequency = <400000>;
};
i2c5: i2c@58785000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clock-frequency = <400000>;
};
i2c6: i2c@58786000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
clocks = <&i2c_clk>;
clock-frequency = <400000>;
};
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld10-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;
};
gic: interrupt-controller@5fe00000 {
compatible = "arm,gic-v3";
reg = <0x5fe00000 0x10000>, /* GICD */
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"
arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi 0 → 120000
View file @ 62c79bb3
../../../../arm/boot/dts/uniphier-pinctrl.dtsi
\ No newline at end of file
arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi 0 → 120000
View file @ 62c79bb3
../../../../arm/boot/dts/uniphier-support-card.dtsi
\ No newline at end of file
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ 62c79bb3
......@@ -133,6 +133,8 @@ gpio: gpio@ff0a0000 {
clocks = <&misc_clk>;
interrupt-parent = <&gic>;
interrupts = <0 16 4>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x1000>;
};
......
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