Commit 636f9d37 authored by Vipul Pandya's avatar Vipul Pandya Committed by David S. Miller

cxgb4: Add support for T4 configuration file

Starting with T4 firmware version 1.3.11.0 the firmware now supports device
configuration via a Firmware Configuration File. The Firmware Configuration
File was primarily developed in order to centralize all of the configuration,
resource allocation, etc. for Unified Wire operation where multiple
Physical / Virtual Function Drivers would be using a T4 adapter simultaneously.

The Firmware Configuration file can live in three locations as shown below
in order of precedence.
1) User defined configuration file: /lib/firmware/cxgb4/t4-config.txt
2) Factory Default configuration file written to FLASH within
   the manufacturing process.
3) Hardwired driver configuration.
Signed-off-by: default avatarJay Hernandez <jay@chelsio.com>
Signed-off-by: default avatarVipul Pandya <vipul@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 52367a76
...@@ -211,6 +211,9 @@ struct tp_err_stats { ...@@ -211,6 +211,9 @@ struct tp_err_stats {
struct tp_params { struct tp_params {
unsigned int ntxchan; /* # of Tx channels */ unsigned int ntxchan; /* # of Tx channels */
unsigned int tre; /* log2 of core clocks per TP tick */ unsigned int tre; /* log2 of core clocks per TP tick */
uint32_t dack_re; /* DACK timer resolution */
unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
}; };
struct vpd_params { struct vpd_params {
...@@ -519,6 +522,8 @@ struct adapter { ...@@ -519,6 +522,8 @@ struct adapter {
struct net_device *port[MAX_NPORTS]; struct net_device *port[MAX_NPORTS];
u8 chan_map[NCHAN]; /* channel -> port map */ u8 chan_map[NCHAN]; /* channel -> port map */
unsigned int l2t_start;
unsigned int l2t_end;
struct l2t_data *l2t; struct l2t_data *l2t;
void *uld_handle[CXGB4_ULD_MAX]; void *uld_handle[CXGB4_ULD_MAX];
struct list_head list_node; struct list_head list_node;
...@@ -683,7 +688,9 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); ...@@ -683,7 +688,9 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len, int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
__be32 *buf); __be32 *buf);
int t4_seeprom_wp(struct adapter *adapter, bool enable); int t4_seeprom_wp(struct adapter *adapter, bool enable);
int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
unsigned int t4_flash_cfg_addr(struct adapter *adapter);
int t4_check_fw_version(struct adapter *adapter); int t4_check_fw_version(struct adapter *adapter);
int t4_prep_adapter(struct adapter *adapter); int t4_prep_adapter(struct adapter *adapter);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
...@@ -698,6 +705,8 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, ...@@ -698,6 +705,8 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
unsigned int mask, unsigned int val);
void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
struct tp_tcp_stats *v6); struct tp_tcp_stats *v6);
void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
...@@ -713,6 +722,12 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, ...@@ -713,6 +722,12 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
int t4_fw_bye(struct adapter *adap, unsigned int mbox); int t4_fw_bye(struct adapter *adap, unsigned int mbox);
int t4_early_init(struct adapter *adap, unsigned int mbox); int t4_early_init(struct adapter *adap, unsigned int mbox);
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
unsigned int mtype, unsigned int maddr,
u32 *finiver, u32 *finicsum, u32 *cfcsum);
int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
unsigned int cache_line_size);
int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
unsigned int vf, unsigned int nparams, const u32 *params, unsigned int vf, unsigned int nparams, const u32 *params,
u32 *val); u32 *val);
......
...@@ -100,6 +100,8 @@ struct tid_info { ...@@ -100,6 +100,8 @@ struct tid_info {
unsigned int nftids; unsigned int nftids;
unsigned int ftid_base; unsigned int ftid_base;
unsigned int aftid_base;
unsigned int aftid_end;
spinlock_t atid_lock ____cacheline_aligned_in_smp; spinlock_t atid_lock ____cacheline_aligned_in_smp;
union aopen_entry *afree; union aopen_entry *afree;
......
This diff is collapsed.
...@@ -115,6 +115,35 @@ ...@@ -115,6 +115,35 @@
#define GLOBALENABLE 0x00000001U #define GLOBALENABLE 0x00000001U
#define SGE_HOST_PAGE_SIZE 0x100c #define SGE_HOST_PAGE_SIZE 0x100c
#define HOSTPAGESIZEPF7_MASK 0x0000000fU
#define HOSTPAGESIZEPF7_SHIFT 28
#define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
#define HOSTPAGESIZEPF6_MASK 0x0000000fU
#define HOSTPAGESIZEPF6_SHIFT 24
#define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
#define HOSTPAGESIZEPF5_MASK 0x0000000fU
#define HOSTPAGESIZEPF5_SHIFT 20
#define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
#define HOSTPAGESIZEPF4_MASK 0x0000000fU
#define HOSTPAGESIZEPF4_SHIFT 16
#define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
#define HOSTPAGESIZEPF3_MASK 0x0000000fU
#define HOSTPAGESIZEPF3_SHIFT 12
#define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
#define HOSTPAGESIZEPF2_MASK 0x0000000fU
#define HOSTPAGESIZEPF2_SHIFT 8
#define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
#define HOSTPAGESIZEPF1_MASK 0x0000000fU
#define HOSTPAGESIZEPF1_SHIFT 4
#define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT)
#define HOSTPAGESIZEPF0_MASK 0x0000000fU #define HOSTPAGESIZEPF0_MASK 0x0000000fU
#define HOSTPAGESIZEPF0_SHIFT 0 #define HOSTPAGESIZEPF0_SHIFT 0
#define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT)
...@@ -162,6 +191,8 @@ ...@@ -162,6 +191,8 @@
#define SGE_INT_ENABLE3 0x1040 #define SGE_INT_ENABLE3 0x1040
#define SGE_FL_BUFFER_SIZE0 0x1044 #define SGE_FL_BUFFER_SIZE0 0x1044
#define SGE_FL_BUFFER_SIZE1 0x1048 #define SGE_FL_BUFFER_SIZE1 0x1048
#define SGE_FL_BUFFER_SIZE2 0x104c
#define SGE_FL_BUFFER_SIZE3 0x1050
#define SGE_INGRESS_RX_THRESHOLD 0x10a0 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
#define THRESHOLD_0_MASK 0x3f000000U #define THRESHOLD_0_MASK 0x3f000000U
#define THRESHOLD_0_SHIFT 24 #define THRESHOLD_0_SHIFT 24
...@@ -367,7 +398,7 @@ ...@@ -367,7 +398,7 @@
#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
#define MEM_WRAP_CLIENT_NUM_SHIFT 0 #define MEM_WRAP_CLIENT_NUM_SHIFT 0
#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
#define MA_PCIE_FW 0x30b8
#define MA_PARITY_ERROR_STATUS 0x77f4 #define MA_PARITY_ERROR_STATUS 0x77f4
#define EDC_0_BASE_ADDR 0x7900 #define EDC_0_BASE_ADDR 0x7900
...@@ -469,6 +500,10 @@ ...@@ -469,6 +500,10 @@
#define TIMERRESOLUTION_MASK 0x00ff0000U #define TIMERRESOLUTION_MASK 0x00ff0000U
#define TIMERRESOLUTION_SHIFT 16 #define TIMERRESOLUTION_SHIFT 16
#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
#define DELAYEDACKRESOLUTION_MASK 0x000000ffU
#define DELAYEDACKRESOLUTION_SHIFT 0
#define DELAYEDACKRESOLUTION_GET(x) \
(((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
#define TP_SHIFT_CNT 0x7dc0 #define TP_SHIFT_CNT 0x7dc0
......
...@@ -155,6 +155,17 @@ struct fw_eth_tx_pkt_vm_wr { ...@@ -155,6 +155,17 @@ struct fw_eth_tx_pkt_vm_wr {
#define FW_CMD_MAX_TIMEOUT 3000 #define FW_CMD_MAX_TIMEOUT 3000
/*
* If a host driver does a HELLO and discovers that there's already a MASTER
* selected, we may have to wait for that MASTER to finish issuing RESET,
* configuration and INITIALIZE commands. Also, there's a possibility that
* our own HELLO may get lost if it happens right as the MASTER is issuign a
* RESET command, so we need to be willing to make a few retries of our HELLO.
*/
#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
#define FW_CMD_HELLO_RETRIES 3
enum fw_cmd_opcodes { enum fw_cmd_opcodes {
FW_LDST_CMD = 0x01, FW_LDST_CMD = 0x01,
FW_RESET_CMD = 0x03, FW_RESET_CMD = 0x03,
...@@ -307,6 +318,10 @@ struct fw_reset_cmd { ...@@ -307,6 +318,10 @@ struct fw_reset_cmd {
__be32 r3; __be32 r3;
}; };
enum fw_hellow_cmd {
fw_hello_cmd_stage_os = 0x0
};
struct fw_hello_cmd { struct fw_hello_cmd {
__be32 op_to_write; __be32 op_to_write;
__be32 retval_len16; __be32 retval_len16;
...@@ -315,8 +330,14 @@ struct fw_hello_cmd { ...@@ -315,8 +330,14 @@ struct fw_hello_cmd {
#define FW_HELLO_CMD_INIT (1U << 30) #define FW_HELLO_CMD_INIT (1U << 30)
#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29) #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
#define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28) #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
#define FW_HELLO_CMD_MBMASTER(x) ((x) << 24) #define FW_HELLO_CMD_MBMASTER_MASK 0xfU
#define FW_HELLO_CMD_MBMASTER_SHIFT 24
#define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
#define FW_HELLO_CMD_MBMASTER_GET(x) \
(((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20) #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
#define FW_HELLO_CMD_STAGE(x) ((x) << 17)
#define FW_HELLO_CMD_CLEARINIT (1U << 16)
__be32 fwrev; __be32 fwrev;
}; };
...@@ -1654,18 +1675,4 @@ struct fw_hdr { ...@@ -1654,18 +1675,4 @@ struct fw_hdr {
#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
#define S_FW_CMD_OP 24
#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
#define S_FW_CMD_REQUEST 23
#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
#define S_FW_CMD_WRITE 21
#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
#define S_FW_LDST_CMD_ADDRSPACE 0
#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
#endif /* _T4FW_INTERFACE_H_ */ #endif /* _T4FW_INTERFACE_H_ */
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