Commit 64954d19 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'samsung-drivers-5.16' of...

Merge tag 'samsung-drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers

Samsung SoC drivers changes for v5.16

1. Convert Exynos ChipID and ASV driver to a module and make it a
   default, instead of selected. The driver is not essential, so it
   could be disabled, if needed.
2. Add support for Exynos850 and Exynos Auto v9 to Exynos ChipID and ASV
   driver.
3. Get rid of HAVE_S3C_RTC because it was adding just another layer
   instead of direct dependencies.
4. Minor cleanups.

* tag 'samsung-drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  soc: samsung: exynos-chipid: add exynosautov9 SoC support
  rtc: s3c: remove HAVE_S3C_RTC in favor of direct dependencies
  soc: samsung: exynos-chipid: Add Exynos850 support
  dt-bindings: samsung: exynos-chipid: Document Exynos850 compatible
  soc: samsung: exynos-chipid: Pass revision reg offsets
  soc: samsung: pm_domains: drop unused is_off field
  arm64: exynos: don't have ARCH_EXYNOS select EXYNOS_CHIPID
  soc: samsung: exynos-chipid: do not enforce built-in
  soc: samsung: exynos-chipid: convert to a module
  soc: samsung: exynos-chipid: avoid soc_device_to_device()
  soc: samsung: exynos-pmu: Fix compilation when nothing selects CONFIG_MFD_CORE

Link: https://lore.kernel.org/r/20211026094709.75692-2-krzysztof.kozlowski@canonical.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c6807970 b417d1e8
...@@ -11,8 +11,9 @@ maintainers: ...@@ -11,8 +11,9 @@ maintainers:
properties: properties:
compatible: compatible:
items: enum:
- const: samsung,exynos4210-chipid - samsung,exynos4210-chipid
- samsung,exynos850-chipid
reg: reg:
maxItems: 1 maxItems: 1
......
...@@ -475,7 +475,6 @@ config ARCH_S3C24XX ...@@ -475,7 +475,6 @@ config ARCH_S3C24XX
select GPIOLIB select GPIOLIB
select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_MULTI_HANDLER
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_IO_H select NEED_MACH_IO_H
select S3C2410_WATCHDOG select S3C2410_WATCHDOG
select SAMSUNG_ATAGS select SAMSUNG_ATAGS
......
...@@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS ...@@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS
select ARM_GIC select ARM_GIC
select EXYNOS_IRQ_COMBINER select EXYNOS_IRQ_COMBINER
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select EXYNOS_CHIPID
select EXYNOS_THERMAL select EXYNOS_THERMAL
select EXYNOS_PMU select EXYNOS_PMU
select EXYNOS_SROM select EXYNOS_SROM
...@@ -22,7 +21,6 @@ menuconfig ARCH_EXYNOS ...@@ -22,7 +21,6 @@ menuconfig ARCH_EXYNOS
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS if PM
......
...@@ -13,7 +13,6 @@ config ARCH_S5PV210 ...@@ -13,7 +13,6 @@ config ARCH_S5PV210
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select GPIOLIB select GPIOLIB
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select SOC_SAMSUNG select SOC_SAMSUNG
......
...@@ -92,10 +92,8 @@ config ARCH_BRCMSTB ...@@ -92,10 +92,8 @@ config ARCH_BRCMSTB
config ARCH_EXYNOS config ARCH_EXYNOS
bool "ARMv8 based Samsung Exynos SoC family" bool "ARMv8 based Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG select COMMON_CLK_SAMSUNG
select EXYNOS_CHIPID
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select EXYNOS_PMU select EXYNOS_PMU
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS if PM
......
...@@ -1404,16 +1404,10 @@ config RTC_DRV_OMAP ...@@ -1404,16 +1404,10 @@ config RTC_DRV_OMAP
This driver can also be built as a module, if so, module This driver can also be built as a module, if so, module
will be called rtc-omap. will be called rtc-omap.
config HAVE_S3C_RTC
bool
help
This will include RTC support for Samsung SoCs. If
you want to include RTC support for any machine, kindly
select this in the respective mach-XXXX/Kconfig file.
config RTC_DRV_S3C config RTC_DRV_S3C
tristate "Samsung S3C series SoC RTC" tristate "Samsung S3C series SoC RTC"
depends on ARCH_S3C64XX || HAVE_S3C_RTC || COMPILE_TEST depends on ARCH_EXYNOS || ARCH_S3C64XX || ARCH_S3C24XX || ARCH_S5PV210 || \
COMPILE_TEST
help help
RTC (Realtime Clock) driver for the clock inbuilt into the RTC (Realtime Clock) driver for the clock inbuilt into the
Samsung S3C24XX series of SoCs. This can provide periodic Samsung S3C24XX series of SoCs. This can provide periodic
......
...@@ -13,18 +13,21 @@ config EXYNOS_ASV_ARM ...@@ -13,18 +13,21 @@ config EXYNOS_ASV_ARM
depends on EXYNOS_CHIPID depends on EXYNOS_CHIPID
config EXYNOS_CHIPID config EXYNOS_CHIPID
bool "Exynos ChipID controller and ASV driver" if COMPILE_TEST tristate "Exynos ChipID controller and ASV driver"
depends on ARCH_EXYNOS || COMPILE_TEST depends on ARCH_EXYNOS || COMPILE_TEST
default ARCH_EXYNOS
select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS
select MFD_SYSCON select MFD_SYSCON
select SOC_BUS select SOC_BUS
help help
Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage.
This driver can also be built as module (exynos_chipid).
config EXYNOS_PMU config EXYNOS_PMU
bool "Exynos PMU controller driver" if COMPILE_TEST bool "Exynos PMU controller driver" if COMPILE_TEST
depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST) depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST)
select EXYNOS_PMU_ARM_DRIVERS if ARM && ARCH_EXYNOS select EXYNOS_PMU_ARM_DRIVERS if ARM && ARCH_EXYNOS
select MFD_CORE
# There is no need to enable these drivers for ARMv8 # There is no need to enable these drivers for ARMv8
config EXYNOS_PMU_ARM_DRIVERS config EXYNOS_PMU_ARM_DRIVERS
......
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o
obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o
exynos_chipid-y += exynos-chipid.o exynos-asv.o
obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o exynos-asv.o
obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
......
...@@ -15,7 +15,9 @@ ...@@ -15,7 +15,9 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/mfd/syscon.h> #include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/slab.h> #include <linux/slab.h>
...@@ -24,6 +26,17 @@ ...@@ -24,6 +26,17 @@
#include "exynos-asv.h" #include "exynos-asv.h"
struct exynos_chipid_variant {
unsigned int rev_reg; /* revision register offset */
unsigned int main_rev_shift; /* main revision offset in rev_reg */
unsigned int sub_rev_shift; /* sub revision offset in rev_reg */
};
struct exynos_chipid_info {
u32 product_id;
u32 revision;
};
static const struct exynos_soc_id { static const struct exynos_soc_id {
const char *name; const char *name;
unsigned int id; unsigned int id;
...@@ -42,6 +55,8 @@ static const struct exynos_soc_id { ...@@ -42,6 +55,8 @@ static const struct exynos_soc_id {
{ "EXYNOS5440", 0xE5440000 }, { "EXYNOS5440", 0xE5440000 },
{ "EXYNOS5800", 0xE5422000 }, { "EXYNOS5800", 0xE5422000 },
{ "EXYNOS7420", 0xE7420000 }, { "EXYNOS7420", 0xE7420000 },
{ "EXYNOS850", 0xE3830000 },
{ "EXYNOSAUTOV9", 0xAAA80000 },
}; };
static const char *product_id_to_soc_id(unsigned int product_id) static const char *product_id_to_soc_id(unsigned int product_id)
...@@ -49,31 +64,57 @@ static const char *product_id_to_soc_id(unsigned int product_id) ...@@ -49,31 +64,57 @@ static const char *product_id_to_soc_id(unsigned int product_id)
int i; int i;
for (i = 0; i < ARRAY_SIZE(soc_ids); i++) for (i = 0; i < ARRAY_SIZE(soc_ids); i++)
if ((product_id & EXYNOS_MASK) == soc_ids[i].id) if (product_id == soc_ids[i].id)
return soc_ids[i].name; return soc_ids[i].name;
return NULL; return NULL;
} }
static int exynos_chipid_get_chipid_info(struct regmap *regmap,
const struct exynos_chipid_variant *data,
struct exynos_chipid_info *soc_info)
{
int ret;
unsigned int val, main_rev, sub_rev;
ret = regmap_read(regmap, EXYNOS_CHIPID_REG_PRO_ID, &val);
if (ret < 0)
return ret;
soc_info->product_id = val & EXYNOS_MASK;
if (data->rev_reg != EXYNOS_CHIPID_REG_PRO_ID) {
ret = regmap_read(regmap, data->rev_reg, &val);
if (ret < 0)
return ret;
}
main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
sub_rev = (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK;
soc_info->revision = (main_rev << EXYNOS_REV_PART_SHIFT) | sub_rev;
return 0;
}
static int exynos_chipid_probe(struct platform_device *pdev) static int exynos_chipid_probe(struct platform_device *pdev)
{ {
const struct exynos_chipid_variant *drv_data;
struct exynos_chipid_info soc_info;
struct soc_device_attribute *soc_dev_attr; struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev; struct soc_device *soc_dev;
struct device_node *root; struct device_node *root;
struct regmap *regmap; struct regmap *regmap;
u32 product_id;
u32 revision;
int ret; int ret;
drv_data = of_device_get_match_data(&pdev->dev);
if (!drv_data)
return -EINVAL;
regmap = device_node_to_regmap(pdev->dev.of_node); regmap = device_node_to_regmap(pdev->dev.of_node);
if (IS_ERR(regmap)) if (IS_ERR(regmap))
return PTR_ERR(regmap); return PTR_ERR(regmap);
ret = regmap_read(regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id); ret = exynos_chipid_get_chipid_info(regmap, drv_data, &soc_info);
if (ret < 0) if (ret < 0)
return ret; return ret;
revision = product_id & EXYNOS_REV_MASK;
soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr), soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr),
GFP_KERNEL); GFP_KERNEL);
if (!soc_dev_attr) if (!soc_dev_attr)
...@@ -86,8 +127,8 @@ static int exynos_chipid_probe(struct platform_device *pdev) ...@@ -86,8 +127,8 @@ static int exynos_chipid_probe(struct platform_device *pdev)
of_node_put(root); of_node_put(root);
soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"%x", revision); "%x", soc_info.revision);
soc_dev_attr->soc_id = product_id_to_soc_id(product_id); soc_dev_attr->soc_id = product_id_to_soc_id(soc_info.product_id);
if (!soc_dev_attr->soc_id) { if (!soc_dev_attr->soc_id) {
pr_err("Unknown SoC\n"); pr_err("Unknown SoC\n");
return -ENODEV; return -ENODEV;
...@@ -104,9 +145,8 @@ static int exynos_chipid_probe(struct platform_device *pdev) ...@@ -104,9 +145,8 @@ static int exynos_chipid_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, soc_dev); platform_set_drvdata(pdev, soc_dev);
dev_info(soc_device_to_device(soc_dev), dev_info(&pdev->dev, "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n",
"Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", soc_dev_attr->soc_id, soc_info.product_id, soc_info.revision);
soc_dev_attr->soc_id, product_id, revision);
return 0; return 0;
...@@ -125,10 +165,29 @@ static int exynos_chipid_remove(struct platform_device *pdev) ...@@ -125,10 +165,29 @@ static int exynos_chipid_remove(struct platform_device *pdev)
return 0; return 0;
} }
static const struct exynos_chipid_variant exynos4210_chipid_drv_data = {
.rev_reg = 0x0,
.main_rev_shift = 4,
.sub_rev_shift = 0,
};
static const struct exynos_chipid_variant exynos850_chipid_drv_data = {
.rev_reg = 0x10,
.main_rev_shift = 20,
.sub_rev_shift = 16,
};
static const struct of_device_id exynos_chipid_of_device_ids[] = { static const struct of_device_id exynos_chipid_of_device_ids[] = {
{ .compatible = "samsung,exynos4210-chipid" }, {
{} .compatible = "samsung,exynos4210-chipid",
.data = &exynos4210_chipid_drv_data,
}, {
.compatible = "samsung,exynos850-chipid",
.data = &exynos850_chipid_drv_data,
},
{ }
}; };
MODULE_DEVICE_TABLE(of, exynos_chipid_of_device_ids);
static struct platform_driver exynos_chipid_driver = { static struct platform_driver exynos_chipid_driver = {
.driver = { .driver = {
...@@ -138,4 +197,11 @@ static struct platform_driver exynos_chipid_driver = { ...@@ -138,4 +197,11 @@ static struct platform_driver exynos_chipid_driver = {
.probe = exynos_chipid_probe, .probe = exynos_chipid_probe,
.remove = exynos_chipid_remove, .remove = exynos_chipid_remove,
}; };
builtin_platform_driver(exynos_chipid_driver); module_platform_driver(exynos_chipid_driver);
MODULE_DESCRIPTION("Samsung Exynos ChipID controller and ASV driver");
MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>");
MODULE_AUTHOR("Pankaj Dubey <pankaj.dubey@samsung.com>");
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
MODULE_LICENSE("GPL");
...@@ -503,3 +503,4 @@ int exynos5422_asv_init(struct exynos_asv *asv) ...@@ -503,3 +503,4 @@ int exynos5422_asv_init(struct exynos_asv *asv)
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(exynos5422_asv_init);
...@@ -28,7 +28,6 @@ struct exynos_pm_domain_config { ...@@ -28,7 +28,6 @@ struct exynos_pm_domain_config {
*/ */
struct exynos_pm_domain { struct exynos_pm_domain {
void __iomem *base; void __iomem *base;
bool is_off;
struct generic_pm_domain pd; struct generic_pm_domain pd;
u32 local_pwr_cfg; u32 local_pwr_cfg;
}; };
......
...@@ -9,10 +9,8 @@ ...@@ -9,10 +9,8 @@
#define __LINUX_SOC_EXYNOS_CHIPID_H #define __LINUX_SOC_EXYNOS_CHIPID_H
#define EXYNOS_CHIPID_REG_PRO_ID 0x00 #define EXYNOS_CHIPID_REG_PRO_ID 0x00
#define EXYNOS_SUBREV_MASK (0xf << 4) #define EXYNOS_REV_PART_MASK 0xf
#define EXYNOS_MAINREV_MASK (0xf << 0) #define EXYNOS_REV_PART_SHIFT 4
#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | \
EXYNOS_MAINREV_MASK)
#define EXYNOS_MASK 0xfffff000 #define EXYNOS_MASK 0xfffff000
#define EXYNOS_CHIPID_REG_PKG_ID 0x04 #define EXYNOS_CHIPID_REG_PKG_ID 0x04
......
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