Commit 64b96917 authored by Ranjani Sridharan's avatar Ranjani Sridharan Committed by Mark Brown

ASoC: SOF: rename cores_mask to host_managed_cores_mask

Rename the cores_mask in struct sof_intel_dsp_desc to
host_managed_cores_mask to be more indicative of the fact that
only these cores can be powered up/down by the host.
Signed-off-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@linux.intel.com>
Reviewed-by: default avatarGuennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: default avatarKeyon Jie <yang.jie@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20200910164125.2033062-2-kai.vehmanen@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent a0822e3e
...@@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = { ...@@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
/* Apollolake */ /* Apollolake */
.cores_num = 2, .cores_num = 2,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1), .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI, .ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE, .ipc_ack = HDA_DSP_REG_HIPCIE,
......
...@@ -655,7 +655,7 @@ EXPORT_SYMBOL_NS(sof_bdw_ops, SND_SOC_SOF_BROADWELL); ...@@ -655,7 +655,7 @@ EXPORT_SYMBOL_NS(sof_bdw_ops, SND_SOC_SOF_BROADWELL);
const struct sof_intel_dsp_desc bdw_chip_info = { const struct sof_intel_dsp_desc bdw_chip_info = {
.cores_num = 1, .cores_num = 1,
.cores_mask = 1, .host_managed_cores_mask = 1,
}; };
EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL); EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL);
......
...@@ -651,7 +651,7 @@ EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD); ...@@ -651,7 +651,7 @@ EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
const struct sof_intel_dsp_desc tng_chip_info = { const struct sof_intel_dsp_desc tng_chip_info = {
.cores_num = 1, .cores_num = 1,
.cores_mask = 1, .host_managed_cores_mask = 1,
}; };
EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD); EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
...@@ -896,7 +896,7 @@ EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL); ...@@ -896,7 +896,7 @@ EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
const struct sof_intel_dsp_desc byt_chip_info = { const struct sof_intel_dsp_desc byt_chip_info = {
.cores_num = 1, .cores_num = 1,
.cores_mask = 1, .host_managed_cores_mask = 1,
}; };
EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL); EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
...@@ -976,7 +976,7 @@ EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL); ...@@ -976,7 +976,7 @@ EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
const struct sof_intel_dsp_desc cht_chip_info = { const struct sof_intel_dsp_desc cht_chip_info = {
.cores_num = 1, .cores_num = 1,
.cores_mask = 1, .host_managed_cores_mask = 1,
}; };
EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL); EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);
......
...@@ -334,7 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { ...@@ -334,7 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
/* Cannonlake */ /* Cannonlake */
.cores_num = 4, .cores_num = 4,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) | .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) | HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) | HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3), HDA_DSP_CORE_MASK(3),
...@@ -353,7 +353,7 @@ const struct sof_intel_dsp_desc icl_chip_info = { ...@@ -353,7 +353,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
/* Icelake */ /* Icelake */
.cores_num = 4, .cores_num = 4,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) | .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) | HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) | HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3), HDA_DSP_CORE_MASK(3),
...@@ -372,7 +372,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { ...@@ -372,7 +372,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
/* Elkhartlake */ /* Elkhartlake */
.cores_num = 4, .cores_num = 4,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0), .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
.ipc_req = CNL_DSP_REG_HIPCIDR, .ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA, .ipc_ack = CNL_DSP_REG_HIPCIDA,
...@@ -388,7 +388,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = { ...@@ -388,7 +388,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
/* Jasperlake */ /* Jasperlake */
.cores_num = 2, .cores_num = 2,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) | .host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1), HDA_DSP_CORE_MASK(1),
.ipc_req = CNL_DSP_REG_HIPCIDR, .ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
......
...@@ -610,7 +610,7 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend) ...@@ -610,7 +610,7 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
#endif #endif
/* power down DSP */ /* power down DSP */
ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask); ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
if (ret < 0) { if (ret < 0) {
dev_err(sdev->dev, dev_err(sdev->dev,
"error: failed to power down core during suspend\n"); "error: failed to power down core during suspend\n");
......
...@@ -91,7 +91,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration) ...@@ -91,7 +91,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
int i; int i;
/* step 1: power up corex */ /* step 1: power up corex */
ret = hda_dsp_core_power_up(sdev, chip->cores_mask); ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
if (ret < 0) { if (ret < 0) {
if (iteration == HDA_FW_BOOT_ATTEMPTS) if (iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
...@@ -147,7 +147,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration) ...@@ -147,7 +147,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
/* step 5: power down corex */ /* step 5: power down corex */
ret = hda_dsp_core_power_down(sdev, ret = hda_dsp_core_power_down(sdev,
chip->cores_mask & ~(HDA_DSP_CORE_MASK(0))); chip->host_managed_cores_mask & ~(HDA_DSP_CORE_MASK(0)));
if (ret < 0) { if (ret < 0) {
if (iteration == HDA_FW_BOOT_ATTEMPTS) if (iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, dev_err(sdev->dev,
...@@ -176,7 +176,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration) ...@@ -176,7 +176,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
err: err:
hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX); hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
hda_dsp_core_reset_power_down(sdev, chip->cores_mask); hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
return ret; return ret;
} }
......
...@@ -928,7 +928,7 @@ int hda_dsp_remove(struct snd_sof_dev *sdev) ...@@ -928,7 +928,7 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
/* disable cores */ /* disable cores */
if (chip) if (chip)
hda_dsp_core_reset_power_down(sdev, chip->cores_mask); hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
/* disable DSP */ /* disable DSP */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
......
...@@ -154,7 +154,7 @@ ...@@ -154,7 +154,7 @@
/* DSP hardware descriptor */ /* DSP hardware descriptor */
struct sof_intel_dsp_desc { struct sof_intel_dsp_desc {
int cores_num; int cores_num;
int cores_mask; int host_managed_cores_mask;
int init_core_mask; /* cores available after fw boot */ int init_core_mask; /* cores available after fw boot */
int ipc_req; int ipc_req;
int ipc_req_mask; int ipc_req_mask;
......
...@@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { ...@@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
/* Tigerlake */ /* Tigerlake */
.cores_num = 4, .cores_num = 4,
.init_core_mask = 1, .init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0), .host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
.ipc_req = CNL_DSP_REG_HIPCIDR, .ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA, .ipc_ack = CNL_DSP_REG_HIPCIDA,
......
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