Commit 64f42cec authored by Vineet Gupta's avatar Vineet Gupta

ARC: create cpu specific version of arch_cpu_idle()

This paves way for creating a 3rd variant needed for NPS ARC700 without
littering ifdey'ery all over the place
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 1112c3b2
......@@ -47,9 +47,6 @@
#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
(ARCV2_IRQ_DEF_PRIO << 1))
/* SLEEP needs default irq priority (<=) which can interrupt the doze */
#define ISA_SLEEP_ARG (0x10 | ARCV2_IRQ_DEF_PRIO)
#ifndef __ASSEMBLY__
/*
......
......@@ -43,8 +43,6 @@
#define ISA_INIT_STATUS_BITS STATUS_IE_MASK
#define ISA_SLEEP_ARG 0x3
#ifndef __ASSEMBLY__
/******************************************************************
......
......@@ -79,15 +79,29 @@ SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new)
return uval;
}
#ifdef CONFIG_ISA_ARCV2
void arch_cpu_idle(void)
{
/* sleep, but enable all interrupts before committing */
/* Re-enable interrupts <= default irq priority before commiting SLEEP */
const unsigned int arg = 0x10 | ARCV2_IRQ_DEF_PRIO;
__asm__ __volatile__(
"sleep %0 \n"
:
:"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const */
:"I"(arg)); /* can't be "r" has to be embedded const */
}
#else
void arch_cpu_idle(void)
{
/* sleep, but enable both set E1/E2 (levels of interrutps) before committing */
__asm__ __volatile__("sleep 0x3 \n");
}
#endif
asmlinkage void ret_from_fork(void);
/*
......
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