Commit 6520e968 authored by Alim Akhtar's avatar Alim Akhtar Committed by Kukjin Kim

clk: exynos5420: Add 5800 specific clocks

Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: default avatarArun Kumar K <arun.kk@samsung.com>
Acked-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 664c6588
* Samsung Exynos5420 Clock Controller * Samsung Exynos5420 Clock Controller
The Exynos5420 clock controller generates and supplies clock to various The Exynos5420 clock controller generates and supplies clock to various
controllers within the Exynos5420 SoC. controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
Required Properties: Required Properties:
- compatible: should be one of the following. - compatible: should be one of the following.
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
- "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
- reg: physical base address of the controller and length of memory mapped - reg: physical base address of the controller and length of memory mapped
region. region.
......
This diff is collapsed.
...@@ -193,6 +193,10 @@ ...@@ -193,6 +193,10 @@
#define CLK_SCLK_ISP_SENSOR0 514 #define CLK_SCLK_ISP_SENSOR0 514
#define CLK_SCLK_ISP_SENSOR1 515 #define CLK_SCLK_ISP_SENSOR1 515
#define CLK_SCLK_ISP_SENSOR2 516 #define CLK_SCLK_ISP_SENSOR2 516
#define CLK_ACLK432_SCALER 517
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
/* mux clocks */ /* mux clocks */
#define CLK_MOUT_HDMI 640 #define CLK_MOUT_HDMI 640
......
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