Commit 6650df3c authored by David Daney's avatar David Daney Committed by Ralf Baechle

MIPS: Move cache setup to setup_arch().

commit 97ce2c88 (jump-label: initialize
jump-label subsystem much earlier) breaks MIPS.  The jump_label_init()
call was moved before trap_init() which is where we initialize
flush_icache_range().

In order to be good citizens, we move cache initialization earlier so
that we don't jump through a null flush_icache_range function pointer
when doing the jump label initialization.
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3822/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9cd9669b
......@@ -14,7 +14,8 @@ extern void *set_vi_handler(int n, vi_handler_t addr);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);
extern void per_cpu_trap_init(bool);
extern void cpu_cache_init(void);
#endif /* __KERNEL__ */
......
......@@ -605,6 +605,8 @@ void __init setup_arch(char **cmdline_p)
resource_init();
plat_smp_setup();
cpu_cache_init();
}
unsigned long kernelsp[NR_CPUS];
......
......@@ -106,7 +106,7 @@ asmlinkage __cpuinit void start_secondary(void)
#endif /* CONFIG_MIPS_MT_SMTC */
cpu_probe();
cpu_report();
per_cpu_trap_init();
per_cpu_trap_init(false);
mips_clockevent_init();
mp_ops->init_secondary();
......
......@@ -1490,7 +1490,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
return set_vi_srs_handler(n, addr, 0);
}
extern void cpu_cache_init(void);
extern void tlb_init(void);
extern void flush_tlb_handlers(void);
......@@ -1517,7 +1516,7 @@ static int __init ulri_disable(char *s)
}
__setup("noulri", ulri_disable);
void __cpuinit per_cpu_trap_init(void)
void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
{
unsigned int cpu = smp_processor_id();
unsigned int status_set = ST0_CU0;
......@@ -1616,7 +1615,9 @@ void __cpuinit per_cpu_trap_init(void)
#ifdef CONFIG_MIPS_MT_SMTC
if (bootTC) {
#endif /* CONFIG_MIPS_MT_SMTC */
cpu_cache_init();
/* Boot CPU's cache setup in setup_arch(). */
if (!is_boot_cpu)
cpu_cache_init();
tlb_init();
#ifdef CONFIG_MIPS_MT_SMTC
} else if (!secondaryTC) {
......@@ -1693,7 +1694,7 @@ void __init trap_init(void)
if (board_ebase_setup)
board_ebase_setup();
per_cpu_trap_init();
per_cpu_trap_init(true);
/*
* Copy the generic exception handlers to their final destination.
......
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