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Commit 665c8ec1 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Patrice Chotard
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ARM: dts: STiH4xx: Simplify clock binding of STiH4xx platforms 

This patch simplifies the clock binding because we had too much detail.
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
parent 443fd7c9
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Showing with 25 additions and 25 deletions
arch/arm/boot/dts/stih407-clock.dtsi
View file @ 665c8ec1
......@@ -42,7 +42,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
......@@ -55,7 +55,7 @@ clockgen_a9_pll: clockgen-a9-pll {
*/
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
compatible = "st,stih407-clkgen-a9-mux";
reg = <0x92b0000 0x10000>;
clocks = <&clockgen_a9_pll 0>,
......@@ -96,7 +96,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -117,7 +117,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
......@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>;
......@@ -199,7 +199,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
......@@ -233,7 +233,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
......@@ -287,7 +287,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
......
arch/arm/boot/dts/stih410-clock.dtsi
View file @ 665c8ec1
......@@ -44,7 +44,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
......@@ -98,7 +98,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -122,7 +122,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
......@@ -140,7 +140,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -150,7 +150,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>;
......@@ -218,7 +218,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
......@@ -254,7 +254,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
......@@ -308,7 +308,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
......
arch/arm/boot/dts/stih418-clock.dtsi
View file @ 665c8ec1
......@@ -44,7 +44,7 @@ clockgen-a9@92b0000 {
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32";
compatible = "st,stih418-clkgen-plla9";
clocks = <&clk_sysin>;
......@@ -98,7 +98,7 @@ clockgen-a@090ff000 {
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -120,7 +120,7 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
compatible = "st,quadfs-pll";
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
......@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll0";
clocks = <&clk_sysin>;
......@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
compatible = "st,clkgen-pll1";
clocks = <&clk_sysin>;
......@@ -212,7 +212,7 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
......@@ -248,7 +248,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
......@@ -309,7 +309,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-D", "st,quadfs";
compatible = "st,quadfs";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
......
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