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Commit 6753ac2b authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu/dce10: simplify hpd code 

use the hpd enum directly as an index
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2285b91c
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Showing with 15 additions and 99 deletions
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
View file @ 6753ac2b
......@@ -330,33 +330,12 @@ static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
enum amdgpu_hpd_id hpd)
{
int idx;
bool connected = false;
switch (hpd) {
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
if (hpd >= adev->mode_info.num_hpd)
return connected;
}
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
connected = true;
......@@ -376,37 +355,16 @@ static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
{
u32 tmp;
bool connected = dce_v10_0_hpd_sense(adev, hpd);
int idx;
switch (hpd) {
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
if (hpd >= adev->mode_info.num_hpd)
return;
}
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
if (connected)
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
else
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
}
/**
......@@ -422,33 +380,12 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
u32 tmp;
int idx;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
switch (amdgpu_connector->hpd.hpd) {
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
}
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
......@@ -457,24 +394,24 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
* https://bugzilla.redhat.com/show_bug.cgi?id=726143
* also avoid interrupt storms during dpms.
*/
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
continue;
}
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
DC_HPD_CONNECT_INT_DELAY,
AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
DC_HPD_DISCONNECT_INT_DELAY,
AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
amdgpu_irq_get(adev, &adev->hpd_irq,
......@@ -495,37 +432,16 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
u32 tmp;
int idx;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
switch (amdgpu_connector->hpd.hpd) {
case AMDGPU_HPD_1:
idx = 0;
break;
case AMDGPU_HPD_2:
idx = 1;
break;
case AMDGPU_HPD_3:
idx = 2;
break;
case AMDGPU_HPD_4:
idx = 3;
break;
case AMDGPU_HPD_5:
idx = 4;
break;
case AMDGPU_HPD_6:
idx = 5;
break;
default:
if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
continue;
}
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
amdgpu_irq_put(adev, &adev->hpd_irq,
amdgpu_connector->hpd.hpd);
......
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