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Commit 682e1c49 authored by Thierry Reding's avatar Thierry Reding
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arm64: tegra: Drop I2C iommus and dma-coherent properties 

Drop the iommus and dma-coherent properties for the I2C controller
device tree nodes. These are only needed for the device tree nodes
that represent the GPC DMA controller, since that is the device
performing the direct memory accesses.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 361238cd
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Showing with 0 additions and 48 deletions
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View file @ 682e1c49
......@@ -674,8 +674,6 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -691,8 +689,6 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -712,8 +708,6 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -747,8 +741,6 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -764,8 +756,6 @@ gen7_i2c: i2c@31c0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -781,8 +771,6 @@ gen9_i2c: i2c@31e0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -1223,8 +1211,6 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -1240,8 +1226,6 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
......
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View file @ 682e1c49
......@@ -809,8 +809,6 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -838,8 +836,6 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -859,8 +855,6 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -880,8 +874,6 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-0 = <&state_dpaux0_i2c>;
pinctrl-1 = <&state_dpaux0_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -901,8 +893,6 @@ dp_aux_ch2_i2c: i2c@31c0000 {
pinctrl-0 = <&state_dpaux2_i2c>;
pinctrl-1 = <&state_dpaux2_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -922,8 +912,6 @@ dp_aux_ch3_i2c: i2c@31e0000 {
pinctrl-0 = <&state_dpaux3_i2c>;
pinctrl-1 = <&state_dpaux3_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -1605,8 +1593,6 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
......@@ -1622,8 +1608,6 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
......
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View file @ 682e1c49
......@@ -697,8 +697,6 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
};
......@@ -718,8 +716,6 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
};
......@@ -739,8 +735,6 @@ dp_aux_ch1_i2c: i2c@3190000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C4>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
};
......@@ -760,8 +754,6 @@ dp_aux_ch0_i2c: i2c@31b0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C6>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
};
......@@ -781,8 +773,6 @@ dp_aux_ch2_i2c: i2c@31c0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
};
......@@ -809,8 +799,6 @@ dp_aux_ch3_i2c: i2c@31e0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
};
......@@ -1700,8 +1688,6 @@ gen2_i2c: i2c@c240000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
};
......@@ -1721,8 +1707,6 @@ gen8_i2c: i2c@c250000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
};
......
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