Commit 683c51ac authored by Dave Jiang's avatar Dave Jiang Committed by Russell King

[ARM PATCH] 2363/1: IQ80332 platform port

Patch from Dave Jiang

Signed-off-by: Dave Jiang

This is the IQ80332 platform port that's based off the IOP33x CPU. The IQ80332 is an PCI-express CRB based off the IOP332 processor. Otherwise functionalites are fairly similar to IQ80331.
Signed-off-by: Russell King
parent cf12055b
This diff is collapsed.
......@@ -25,6 +25,13 @@ config ARCH_IQ80331
Say Y here if you want to run your kernel on the Intel IQ80331
evaluation kit for the IOP331 chipset.
config MACH_IQ80332
bool "Enable support for IQ80332"
select ARCH_IOP331
help
Say Y here if you want to run your kernel on the Intel IQ80332
evaluation kit for the IOP332 chipset
config ARCH_EP80219
bool "Enable support for EP80219"
select ARCH_IOP321
......@@ -41,10 +48,16 @@ config ARCH_IOP331
bool
default ARCH_IQ80331
help
The IQ80331 uses the IOP331 variant.
The IQ80331, IQ80332, and IQ80333 uses the IOP331 variant.
comment "IOP3xx Chipset Features"
endmenu
config IOP331_STEPD
bool "Chip stepping D of the IOP80331 processor or IOP80333"
depends on (ARCH_IOP331)
help
Say Y here if you have StepD of the IOP80331 or IOP8033
based platforms.
endmenu
endif
......@@ -19,3 +19,5 @@ obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o
obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o
obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o
obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o
......@@ -12,6 +12,7 @@
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/config.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/device.h>
......@@ -42,13 +43,13 @@ static struct map_desc iop331_std_desc[] __initdata = {
{ IOP331_VIRT_MEM_BASE, IOP331_PHYS_MEM_BASE, 0x00002000, MT_DEVICE },
/* PCI IO space */
{ 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
{ IOP331_PCI_LOWER_IO_VA, IOP331_PCI_LOWER_IO_PA, IOP331_PCI_IO_WINDOW_SIZE, MT_DEVICE }
};
static struct uart_port iop331_serial_ports[] = {
{
.membase = (char*)(IQ80331_UART0_VIRT),
.mapbase = (IQ80331_UART0_PHYS),
.membase = (char*)(IOP331_UART0_VIRT),
.mapbase = (IOP331_UART0_PHYS),
.irq = IRQ_IOP331_UART0,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
......@@ -58,8 +59,8 @@ static struct uart_port iop331_serial_ports[] = {
.type = PORT_XSCALE,
.fifosize = 32
} , {
.membase = (char*)(IQ80331_UART1_VIRT),
.mapbase = (IQ80331_UART1_PHYS),
.membase = (char*)(IOP331_UART1_VIRT),
.mapbase = (IOP331_UART1_PHYS),
.irq = IRQ_IOP331_UART1,
.flags = UPF_SKIP_TEST,
.iotype = UPIO_MEM,
......@@ -71,6 +72,60 @@ static struct uart_port iop331_serial_ports[] = {
}
};
static struct resource iop33x_i2c_0_resources[] = {
[0] = {
.start = 0xfffff680,
.end = 0xfffff698,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_I2C_0,
.end = IRQ_IOP331_I2C_0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop33x_i2c_1_resources[] = {
[0] = {
.start = 0xfffff6a0,
.end = 0xfffff6b8,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP331_I2C_1,
.end = IRQ_IOP331_I2C_1,
.flags = IORESOURCE_IRQ
}
};
static struct platform_device iop33x_i2c_0_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop33x_i2c_0_resources
};
static struct platform_device iop33x_i2c_1_controller = {
.name = "IOP3xx-I2C",
.id = 1,
.num_resources = 2,
.resource = iop33x_i2c_1_resources
};
static struct platform_device *iop33x_devices[] __initdata = {
&iop33x_i2c_0_controller,
&iop33x_i2c_1_controller
};
void __init iop33x_init(void)
{
if(iop_is_331())
{
platform_add_devices(iop33x_devices,
ARRAY_SIZE(iop33x_devices));
}
}
void __init iop331_map_io(void)
{
iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc));
......@@ -78,22 +133,43 @@ void __init iop331_map_io(void)
early_serial_setup(&iop331_serial_ports[1]);
}
#ifdef CONFIG_ARCH_IQ80331
#ifdef CONFIG_ARCH_IOP331
extern void iop331_init_irq(void);
extern struct sys_timer iop331_timer;
#endif
#ifdef CONFIG_ARCH_IQ80331
extern void iq80331_map_io(void);
#endif
#ifdef CONFIG_MACH_IQ80332
extern void iq80332_map_io(void);
#endif
#if defined(CONFIG_ARCH_IQ80331)
MACHINE_START(IQ80331, "Intel IQ80331")
MAINTAINER("Intel Corp.")
BOOT_MEM(PHYS_OFFSET, 0xfefff000, 0xfffff000) // virtual, physical
//BOOT_MEM(PHYS_OFFSET, IQ80331_UART0_VIRT, IQ80331_UART0_PHYS)
//BOOT_MEM(PHYS_OFFSET, IOP331_UART0_VIRT, IOP331_UART0_PHYS)
MAPIO(iq80331_map_io)
INITIRQ(iop331_init_irq)
.timer = &iop331_timer,
.timer = &iop331_timer,
BOOT_PARAMS(0x0100)
INIT_MACHINE(iop33x_init)
MACHINE_END
#elif defined(CONFIG_MACH_IQ80332)
MACHINE_START(IQ80332, "Intel IQ80332")
MAINTAINER("Intel Corp.")
BOOT_MEM(PHYS_OFFSET, 0xfefff000, 0xfffff000) // virtual, physical
//BOOT_MEM(PHYS_OFFSET, IOP331_UART0_VIRT, IOP331_UART0_PHYS)
MAPIO(iq80332_map_io)
INITIRQ(iop331_init_irq)
.timer = &iop331_timer,
BOOT_PARAMS(0x0100)
INIT_MACHINE(iop33x_init)
MACHINE_END
#else
#error No machine descriptor defined for this IOP3XX implementation
#endif
......
/*
* linux/arch/arm/mach-iop3xx/mm.c
*
* Low level memory initialization for iq80332 platform
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
/*
* IQ80332 specific IO mappings
*
* We use RedBoot's setup for the onboard devices.
*/
void __init iq80332_map_io(void)
{
iop331_map_io();
}
/*
* arch/arm/mach-iop3xx/iq80332-pci.c
*
* PCI support for the Intel IQ80332 reference board
*
* Author: Dave Jiang <dave.jiang@intel.com>
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
/*
* The following macro is used to lookup irqs in a standard table
* format for those systems that do not already have PCI
* interrupts properly routed. We assume 1 <= pin <= 4
*/
#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \
({ int _ctl_ = -1; \
unsigned int _idsel = idsel - minid; \
if (_idsel <= maxid) \
_ctl_ = pci_irq_table[_idsel][pin-1]; \
_ctl_; })
#define INTA IRQ_IQ80332_INTA
#define INTB IRQ_IQ80332_INTB
#define INTC IRQ_IQ80332_INTC
#define INTD IRQ_IQ80332_INTD
//#define INTE IRQ_IQ80332_I82544
static inline int __init
iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
static int pci_irq_table[][8] = {
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{-1, -1, -1, -1},
{-1, -1, -1, -1},
{-1, -1, -1, -1},
{INTA, INTB, INTC, INTD}, /* PCI-X Slot */
{-1, -1, -1, -1},
{INTC, INTC, INTC, INTC}, /* GigE */
{-1, -1, -1, -1},
{-1, -1, -1, -1},
};
BUG_ON(pin < 1 || pin > 4);
return PCI_IRQ_TABLE_LOOKUP(1, 7);
}
static int iq80332_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if(nr != 0)
return 0;
res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
memset(res, 0, sizeof(struct resource) * 2);
res[0].start = IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].end = IOP331_PCI_UPPER_IO_BA + IOP331_PCI_IO_OFFSET;
res[0].name = "IQ80332 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].end = IOP331_PCI_UPPER_MEM_BA + IOP331_PCI_MEM_OFFSET;
res[1].name = "IQ80332 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->mem_offset = IOP331_PCI_MEM_OFFSET;
sys->io_offset = IOP331_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
iop3xx_pcibios_min_io = IOP331_PCI_LOWER_IO_VA;
iop3xx_pcibios_min_mem = IOP331_PCI_LOWER_MEM_VA;
return 1;
}
static void iq80332_preinit(void)
{
iop331_init();
}
static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iq80332_setup,
.scan = iop331_scan_bus,
.preinit = iq80332_preinit,
.map_irq = iq80332_map_irq
};
static int __init iq80332_pci_init(void)
{
if (machine_is_iq80332())
pci_common_init(&iq80332_pci);
return 0;
}
subsys_initcall(iq80332_pci_init);
......@@ -754,8 +754,8 @@ __8032x_proc_info:
.type __8033x_proc_info,#object
__8033x_proc_info:
.long 0x69054090
.long 0xffffffb0
.long 0x69054010
.long 0xffffff30
.long PMD_TYPE_SECT | \
PMD_SECT_BUFFERABLE | \
PMD_SECT_CACHEABLE | \
......
......@@ -52,5 +52,6 @@ extern unsigned int processor_id;
#include "iq80321.h"
#include "iq31244.h"
#include "iq80331.h"
#include "iq80332.h"
#endif /* _ASM_ARCH_HARDWARE_H */
......@@ -91,6 +91,7 @@
#define NR_IRQS NR_IOP331_IRQS
#if defined(CONFIG_ARCH_IQ80331)
/*
* Interrupts available on the IQ80331 board
*/
......@@ -110,4 +111,26 @@
#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
#elif defined(CONFIG_MACH_IQ80332)
/*
* Interrupts available on the IQ80332 board
*/
/*
* On board devices
*/
#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
/*
* PCI interrupts
*/
#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
#endif
#endif // _IOP331_IRQ_H_
/*
* linux/include/asm/arch-iop3xx/iq80332.h
*
* Intel IQ80332 evaluation board registers
*/
#ifndef _IQ80332_H_
#define _IQ80332_H_
#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
#define IQ80332_FLASHSIZE 0x00800000
#define IQ80332_FLASHWIDTH 1
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
#ifndef __ASSEMBLY__
extern void iq80332_map_io(void);
#endif
#endif // _IQ80332_H_
......@@ -10,7 +10,7 @@
#define CLOCK_TICK_RATE IOP321_TICK_RATE
#elif defined(CONFIG_ARCH_IQ80331)
#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
#define CLOCK_TICK_RATE IOP331_TICK_RATE
......
......@@ -9,8 +9,10 @@
#ifdef CONFIG_ARCH_IOP321
#define UTYPE unsigned char *
#else
#elif defined(CONFIG_ARCH_IOP331)
#define UTYPE u32 *
#else
#error "Missing IOP3xx arch type def"
#endif
static volatile UTYPE uart_base;
......@@ -42,8 +44,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
uart_base = (volatile UTYPE)IQ80321_UART;
else if(machine_is_iq31244())
uart_base = (volatile UTYPE)IQ31244_UART;
else if(machine_is_iq80331())
uart_base = (volatile UTYPE)IQ80331_UART0_PHYS;
else if(machine_is_iq80331() || machine_is_iq80332())
uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
else
uart_base = (volatile UTYPE)0xfe800000;
}
......
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