Commit 68e8fa46 authored by Bjorn Helgaas's avatar Bjorn Helgaas

Merge branch 'pci/host-rockchip' into next

* pci/host-rockchip:
  PCI: rockchip: Fix platform_get_irq() error handling
  PCI: rockchip: Umap IO space if probe fails
  PCI: rockchip: Remove IRQ domain if probe fails
  PCI: rockchip: Disable vpcie0v9 if resume_noirq fails
  PCI: rockchip: Clean up PHY if driver probe or resume fails
  PCI: rockchip: Factor out rockchip_pcie_deinit_phys()
  PCI: rockchip: Factor out rockchip_pcie_disable_clocks()
  PCI: rockchip: Factor out rockchip_pcie_enable_clocks()
  PCI: rockchip: Factor out rockchip_pcie_setup_irq()
  PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders
  PCI: rockchip: Use PCI_NUM_INTX
  PCI: rockchip: Explicitly request exclusive reset control
  dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model
  dt-bindings: PCI: rockchip: Convert to per-lane PHY model
  arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339
  PCI: rockchip: Idle inactive PHY(s)
  phy: rockchip-pcie: Reconstruct driver to support per-lane PHYs
  PCI: rockchip: Add per-lane PHY support
  PCI: rockchip: Factor out rockchip_pcie_get_phys()
  PCI: rockchip: Control optional 12v power supply
  dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controller
parents 3d499a95 81edd471
...@@ -19,8 +19,6 @@ Required properties: ...@@ -19,8 +19,6 @@ Required properties:
- "pm" - "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated - msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. See ./pci-msi.txt msi-specifier data. See ./pci-msi.txt
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
- phy-names: MUST be "pcie-phy".
- interrupts: Three interrupt entries must be specified. - interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names - interrupt-names: Must include the following names
- "sys" - "sys"
...@@ -42,11 +40,24 @@ Required properties: ...@@ -42,11 +40,24 @@ Required properties:
interrupt source. The value must be 1. interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties - interrupt-map-mask and interrupt-map: standard PCI properties
Required properties for legacy PHY model (deprecated):
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
- phy-names: MUST be "pcie-phy".
Required properties for per-lane PHY model (preferred):
- phys: Must contain an phandle to a PHY for each entry in phy-names.
- phy-names: Must include 4 entries for all 4 lanes even if some of
them won't be used for your cases. Entries are of the form "pcie-phy-N":
where N ranges from 0 to 3.
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
for changing the #phy-cells of phy node to support it)
Optional Property: Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY. using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset gpio - ep-gpios: contain the entry for pre-reset gpio
- num-lanes: number of lanes to use - num-lanes: number of lanes to use
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
...@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 { ...@@ -95,6 +106,7 @@ pcie0: pcie@f8000000 {
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe", reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk"; "pm", "pclk", "aclk";
/* deprecated legacy PHY model */
phys = <&pcie_phy>; phys = <&pcie_phy>;
phy-names = "pcie-phy"; phy-names = "pcie-phy";
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 { ...@@ -111,3 +123,13 @@ pcie0: pcie@f8000000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
}; };
}; };
pcie0: pcie@f8000000 {
...
/* preferred per-lane PHY model */
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
...
};
...@@ -3,7 +3,6 @@ Rockchip PCIE PHY ...@@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties: Required properties:
- compatible: rockchip,rk3399-pcie-phy - compatible: rockchip,rk3399-pcie-phy
- #phy-cells: must be 0
- clocks: Must contain an entry in clock-names. - clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk" - clock-names: Must be "refclk"
...@@ -11,6 +10,12 @@ Required properties: ...@@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details. See ../reset/reset.txt for details.
- reset-names: Must be "phy" - reset-names: Must be "phy"
Required properties for legacy PHY mode (deprecated):
- #phy-cells: must be 0
Required properties for per-lane PHY mode (preferred):
- #phy-cells: must be 1
Example: Example:
grf: syscon@ff770000 { grf: syscon@ff770000 {
......
...@@ -238,8 +238,10 @@ pcie0: pcie@f8000000 { ...@@ -238,8 +238,10 @@ pcie0: pcie@f8000000 {
linux,pci-domain = <0>; linux,pci-domain = <0>;
max-link-speed = <1>; max-link-speed = <1>;
msi-map = <0x0 &its 0x0 0x1000>; msi-map = <0x0 &its 0x0 0x1000>;
phys = <&pcie_phy>; phys = <&pcie_phy 0>, <&pcie_phy 1>,
phy-names = "pcie-phy"; <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
...@@ -1295,7 +1297,7 @@ pcie_phy: pcie-phy { ...@@ -1295,7 +1297,7 @@ pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy"; compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>; clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk"; clock-names = "refclk";
#phy-cells = <0>; #phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>; resets = <&cru SRST_PCIEPHY>;
reset-names = "phy"; reset-names = "phy";
status = "disabled"; status = "disabled";
......
This diff is collapsed.
...@@ -73,10 +73,38 @@ struct rockchip_pcie_data { ...@@ -73,10 +73,38 @@ struct rockchip_pcie_data {
struct rockchip_pcie_phy { struct rockchip_pcie_phy {
struct rockchip_pcie_data *phy_data; struct rockchip_pcie_data *phy_data;
struct regmap *reg_base; struct regmap *reg_base;
struct phy_pcie_instance {
struct phy *phy;
u32 index;
} phys[PHY_MAX_LANE_NUM];
struct mutex pcie_mutex;
struct reset_control *phy_rst; struct reset_control *phy_rst;
struct clk *clk_pciephy_ref; struct clk *clk_pciephy_ref;
int pwr_cnt;
int init_cnt;
}; };
static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
{
return container_of(inst, struct rockchip_pcie_phy,
phys[inst->index]);
}
static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
if (args->args_count == 0)
return rk_phy->phys[0].phy;
if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
return ERR_PTR(-ENODEV);
return rk_phy->phys[args->args[0]].phy;
}
static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy, static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
u32 addr, u32 data) u32 addr, u32 data)
{ {
...@@ -116,29 +144,59 @@ static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy, ...@@ -116,29 +144,59 @@ static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
static int rockchip_pcie_phy_power_off(struct phy *phy) static int rockchip_pcie_phy_power_off(struct phy *phy)
{ {
struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); struct phy_pcie_instance *inst = phy_get_drvdata(phy);
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
int err = 0; int err = 0;
mutex_lock(&rk_phy->pcie_mutex);
regmap_write(rk_phy->reg_base,
rk_phy->phy_data->pcie_laneoff,
HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT + inst->index));
if (--rk_phy->pwr_cnt)
goto err_out;
err = reset_control_assert(rk_phy->phy_rst); err = reset_control_assert(rk_phy->phy_rst);
if (err) { if (err) {
dev_err(&phy->dev, "assert phy_rst err %d\n", err); dev_err(&phy->dev, "assert phy_rst err %d\n", err);
return err; goto err_restore;
} }
err_out:
mutex_unlock(&rk_phy->pcie_mutex);
return 0; return 0;
err_restore:
rk_phy->pwr_cnt++;
regmap_write(rk_phy->reg_base,
rk_phy->phy_data->pcie_laneoff,
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT + inst->index));
mutex_unlock(&rk_phy->pcie_mutex);
return err;
} }
static int rockchip_pcie_phy_power_on(struct phy *phy) static int rockchip_pcie_phy_power_on(struct phy *phy)
{ {
struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); struct phy_pcie_instance *inst = phy_get_drvdata(phy);
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
int err = 0; int err = 0;
u32 status; u32 status;
unsigned long timeout; unsigned long timeout;
mutex_lock(&rk_phy->pcie_mutex);
if (rk_phy->pwr_cnt++)
goto err_out;
err = reset_control_deassert(rk_phy->phy_rst); err = reset_control_deassert(rk_phy->phy_rst);
if (err) { if (err) {
dev_err(&phy->dev, "deassert phy_rst err %d\n", err); dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
return err; goto err_pwr_cnt;
} }
regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
...@@ -146,6 +204,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) ...@@ -146,6 +204,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT)); PHY_CFG_ADDR_SHIFT));
regmap_write(rk_phy->reg_base,
rk_phy->phy_data->pcie_laneoff,
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT + inst->index));
/* /*
* No documented timeout value for phy operation below, * No documented timeout value for phy operation below,
* so we make it large enough here. And we use loop-break * so we make it large enough here. And we use loop-break
...@@ -214,18 +278,29 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) ...@@ -214,18 +278,29 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
goto err_pll_lock; goto err_pll_lock;
} }
err_out:
mutex_unlock(&rk_phy->pcie_mutex);
return 0; return 0;
err_pll_lock: err_pll_lock:
reset_control_assert(rk_phy->phy_rst); reset_control_assert(rk_phy->phy_rst);
err_pwr_cnt:
rk_phy->pwr_cnt--;
mutex_unlock(&rk_phy->pcie_mutex);
return err; return err;
} }
static int rockchip_pcie_phy_init(struct phy *phy) static int rockchip_pcie_phy_init(struct phy *phy)
{ {
struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); struct phy_pcie_instance *inst = phy_get_drvdata(phy);
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
int err = 0; int err = 0;
mutex_lock(&rk_phy->pcie_mutex);
if (rk_phy->init_cnt++)
goto err_out;
err = clk_prepare_enable(rk_phy->clk_pciephy_ref); err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
if (err) { if (err) {
dev_err(&phy->dev, "Fail to enable pcie ref clock.\n"); dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
...@@ -238,20 +313,33 @@ static int rockchip_pcie_phy_init(struct phy *phy) ...@@ -238,20 +313,33 @@ static int rockchip_pcie_phy_init(struct phy *phy)
goto err_reset; goto err_reset;
} }
return err; err_out:
mutex_unlock(&rk_phy->pcie_mutex);
return 0;
err_reset: err_reset:
clk_disable_unprepare(rk_phy->clk_pciephy_ref); clk_disable_unprepare(rk_phy->clk_pciephy_ref);
err_refclk: err_refclk:
rk_phy->init_cnt--;
mutex_unlock(&rk_phy->pcie_mutex);
return err; return err;
} }
static int rockchip_pcie_phy_exit(struct phy *phy) static int rockchip_pcie_phy_exit(struct phy *phy)
{ {
struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); struct phy_pcie_instance *inst = phy_get_drvdata(phy);
struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
mutex_lock(&rk_phy->pcie_mutex);
if (--rk_phy->init_cnt)
goto err_init_cnt;
clk_disable_unprepare(rk_phy->clk_pciephy_ref); clk_disable_unprepare(rk_phy->clk_pciephy_ref);
err_init_cnt:
mutex_unlock(&rk_phy->pcie_mutex);
return 0; return 0;
} }
...@@ -283,10 +371,11 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev) ...@@ -283,10 +371,11 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct rockchip_pcie_phy *rk_phy; struct rockchip_pcie_phy *rk_phy;
struct phy *generic_phy;
struct phy_provider *phy_provider; struct phy_provider *phy_provider;
struct regmap *grf; struct regmap *grf;
const struct of_device_id *of_id; const struct of_device_id *of_id;
int i;
u32 phy_num;
grf = syscon_node_to_regmap(dev->parent->of_node); grf = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(grf)) { if (IS_ERR(grf)) {
...@@ -305,6 +394,8 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev) ...@@ -305,6 +394,8 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data; rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
rk_phy->reg_base = grf; rk_phy->reg_base = grf;
mutex_init(&rk_phy->pcie_mutex);
rk_phy->phy_rst = devm_reset_control_get(dev, "phy"); rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
if (IS_ERR(rk_phy->phy_rst)) { if (IS_ERR(rk_phy->phy_rst)) {
if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER) if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
...@@ -319,14 +410,26 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev) ...@@ -319,14 +410,26 @@ static int rockchip_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(rk_phy->clk_pciephy_ref); return PTR_ERR(rk_phy->clk_pciephy_ref);
} }
generic_phy = devm_phy_create(dev, dev->of_node, &ops); /* parse #phy-cells to see if it's legacy PHY model */
if (IS_ERR(generic_phy)) { if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
dev_err(dev, "failed to create PHY\n"); return -ENOENT;
return PTR_ERR(generic_phy);
phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
dev_dbg(dev, "phy number is %d\n", phy_num);
for (i = 0; i < phy_num; i++) {
rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
if (IS_ERR(rk_phy->phys[i].phy)) {
dev_err(dev, "failed to create PHY%d\n", i);
return PTR_ERR(rk_phy->phys[i].phy);
}
rk_phy->phys[i].index = i;
phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
} }
phy_set_drvdata(generic_phy, rk_phy); platform_set_drvdata(pdev, rk_phy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); phy_provider = devm_of_phy_provider_register(dev,
rockchip_pcie_phy_of_xlate);
return PTR_ERR_OR_ZERO(phy_provider); return PTR_ERR_OR_ZERO(phy_provider);
} }
......
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