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Merge tag 'actions-arm64-dt-for-4.20' of... 

Merge tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt

Actions Semi arm64 based SoC DT for v4.20

This updates SPDX headers for remaining files.

For S900 it adds clock, pinctrl, i2c and dma nodes.
S900 SPS is added via topic branch (shared with driver).

For S700 it adds clock nodes.

* tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
  arm64: dts: actions: s700: Set UART clock references from CMU
  arm64: dts: actions: s700: Add Clock Management Unit
  arm64: dts: actions: s900: Add DMA Controller
  arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2
  arm64: dts: actions: s900: Add I2C controller nodes
  arm64: dts: actions: s900-bubblegum-96: Add gpio line names
  arm64: dts: actions: s900: Add gpio properties to pinctrl node
  arm64: dts: actions: s900: Add pinctrl node
  arm64: dts: actions: s900: Add SPS node
  arm64: dts: actions: s900: Source CMU clock for UARTs
  arm64: dts: actions: s900: Add Clock Management Unit nodes
  dt-bindings: power: Add Actions Semi S900 SPS
  arm64: dts: actions: Convert to new-style SPDX license identifiers
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 6a2340c9 01463ac6
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Showing with 381 additions and 16 deletions
Documentation/devicetree/bindings/power/actions,owl-sps.txt
View file @ 6a11b180
......@@ -3,11 +3,13 @@ Actions Semi Owl Smart Power System (SPS)
Required properties:
- compatible : "actions,s500-sps" for S500
"actions,s700-sps" for S700
"actions,s900-sps" for S900
- reg : Offset and length of the register set for the device.
- #power-domain-cells : Must be 1.
See macros in:
include/dt-bindings/power/owl-s500-powergate.h for S500
include/dt-bindings/power/owl-s700-powergate.h for S700
include/dt-bindings/power/owl-s900-powergate.h for S900
Example:
......
arch/arm64/boot/dts/actions/Makefile
View file @ 6a11b180
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb
dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
arch/arm64/boot/dts/actions/s700-cubieboard7.dts
View file @ 6a11b180
......@@ -28,12 +28,6 @@ memory@1,e0000000 {
device_type = "memory";
reg = <0x1 0xe0000000 0x0 0x0>;
};
uart3_clk: uart3-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&timer {
......@@ -42,5 +36,4 @@ &timer {
&uart3 {
status = "okay";
clocks = <&uart3_clk>;
};
arch/arm64/boot/dts/actions/s700.dtsi
View file @ 6a11b180
......@@ -3,6 +3,7 @@
* Copyright (c) 2017 Andreas Färber
*/
#include <dt-bindings/clock/actions,s700-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
......@@ -87,6 +88,12 @@ hosc: hosc {
#clock-cells = <0>;
};
losc: losc {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
......@@ -107,6 +114,7 @@ gic: interrupt-controller@e00f1000 {
uart0: serial@e0120000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0120000 0x0 0x2000>;
clocks = <&cmu CLK_UART0>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -114,6 +122,7 @@ uart0: serial@e0120000 {
uart1: serial@e0122000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0122000 0x0 0x2000>;
clocks = <&cmu CLK_UART1>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -121,6 +130,7 @@ uart1: serial@e0122000 {
uart2: serial@e0124000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0124000 0x0 0x2000>;
clocks = <&cmu CLK_UART2>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -128,6 +138,7 @@ uart2: serial@e0124000 {
uart3: serial@e0126000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
clocks = <&cmu CLK_UART3>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -135,6 +146,7 @@ uart3: serial@e0126000 {
uart4: serial@e0128000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0128000 0x0 0x2000>;
clocks = <&cmu CLK_UART4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -142,6 +154,7 @@ uart4: serial@e0128000 {
uart5: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
clocks = <&cmu CLK_UART5>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -149,10 +162,18 @@ uart5: serial@e012a000 {
uart6: serial@e012c000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012c000 0x0 0x2000>;
clocks = <&cmu CLK_UART6>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
cmu: clock-controller@e0168000 {
compatible = "actions,s700-cmu";
reg = <0x0 0xe0168000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
};
sps: power-controller@e01b0100 {
compatible = "actions,s700-sps";
reg = <0x0 0xe01b0100 0x0 0x100>;
......
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
View file @ 6a11b180
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
......@@ -24,11 +23,223 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&i2c0 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_default>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_default>;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_default>;
};
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "Schematics Bubblegum96"
* version v1.0
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Boards naming of a line and the schematic name of
* the same line are in conflict, the 96Boards specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART2. Only exception is the I2C lines for which the schematic
* naming has been preferred. This is only for the informational
* lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
* are the only ones actually used for GPIO.
*/
&pinctrl {
gpio-line-names =
"GPIO-A", /* GPIO_0, LSEC pin 23 */
"GPIO-B", /* GPIO_1, LSEC pin 24 */
"GPIO-C", /* GPIO_2, LSEC pin 25 */
"GPIO-D", /* GPIO_3, LSEC pin 26 */
"GPIO-E", /* GPIO_4, LSEC pin 27 */
"GPIO-F", /* GPIO_5, LSEC pin 28 */
"GPIO-G", /* GPIO_6, LSEC pin 29 */
"GPIO-H", /* GPIO_7, LSEC pin 30 */
"GPIO-I", /* GPIO_8, LSEC pin 31 */
"GPIO-J", /* GPIO_9, LSEC pin 32 */
"NC", /* GPIO_10 */
"NC", /* GPIO_11 */
"SIRQ2_1V8", /* GPIO_12 */
"PCM0_OUT", /* GPIO_13 */
"WIFI_LED", /* GPIO_14 */
"PCM0_SYNC", /* GPIO_15 */
"PCM0_CLK", /* GPIO_16 */
"PCM0_IN", /* GPIO_17 */
"BT_LED", /* GPIO_18 */
"LED0", /* GPIO_19 */
"LED1", /* GPIO_20 */
"JTAG_TCK", /* GPIO_21 */
"JTAG_TMS", /* GPIO_22 */
"JTAG_TDI", /* GPIO_23 */
"JTAG_TDO", /* GPIO_24 */
"[UART1_RxD]", /* GPIO_25, LSEC pin 13 */
"NC", /* GPIO_26 */
"[UART1_TxD]", /* GPIO_27, LSEC pin 11 */
"SD0_D0", /* GPIO_28 */
"SD0_D1", /* GPIO_29 */
"SD0_D2", /* GPIO_30 */
"SD0_D3", /* GPIO_31 */
"SD1_D0", /* GPIO_32 */
"SD1_D1", /* GPIO_33 */
"SD1_D2", /* GPIO_34 */
"SD1_D3", /* GPIO_35 */
"SD0_CMD", /* GPIO_36 */
"SD0_CLK", /* GPIO_37 */
"SD1_CMD", /* GPIO_38 */
"SD1_CLK", /* GPIO_39 */
"SPI0_SCLK", /* GPIO_40, LSEC pin 8 */
"SPI0_CS", /* GPIO_41, LSEC pin 12 */
"SPI0_DIN", /* GPIO_42, LSEC pin 10 */
"SPI0_DOUT", /* GPIO_43, LSEC pin 14 */
"I2C5_SDATA", /* GPIO_44, HSEC pin 36 */
"I2C5_SCLK", /* GPIO_45, HSEC pin 38 */
"UART0_RX", /* GPIO_46, LSEC pin 7 */
"UART0_TX", /* GPIO_47, LSEC pin 5 */
"UART0_RTSB", /* GPIO_48, LSEC pin 9 */
"UART0_CTSB", /* GPIO_49, LSEC pin 3 */
"I2C4_SCLK", /* GPIO_50, HSEC pin 32 */
"I2C4_SDATA", /* GPIO_51, HSEC pin 34 */
"I2C0_SCLK", /* GPIO_52 */
"I2C0_SDATA", /* GPIO_53 */
"I2C1_SCLK", /* GPIO_54, LSEC pin 15 */
"I2C1_SDATA", /* GPIO_55, LSEC pin 17 */
"I2C2_SCLK", /* GPIO_56, LSEC pin 19 */
"I2C2_SDATA", /* GPIO_57, LSEC pin 21 */
"CSI0_DN0", /* GPIO_58, HSEC pin 10 */
"CSI0_DP0", /* GPIO_59, HSEC pin 8 */
"CSI0_DN1", /* GPIO_60, HSEC pin 16 */
"CSI0_DP1", /* GPIO_61, HSEC pin 14 */
"CSI0_CN", /* GPIO_62, HSEC pin 4 */
"CSI0_CP", /* GPIO_63, HSEC pin 2 */
"CSI0_DN2", /* GPIO_64, HSEC pin 22 */
"CSI0_DP2", /* GPIO_65, HSEC pin 20 */
"CSI0_DN3", /* GPIO_66, HSEC pin 28 */
"CSI0_DP3", /* GPIO_67, HSEC pin 26 */
"[CLK0]", /* GPIO_68, HSEC pin 15 */
"CSI1_DN0", /* GPIO_69, HSEC pin 44 */
"CSI1_DP0", /* GPIO_70, HSEC pin 42 */
"CSI1_DN1", /* GPIO_71, HSEC pin 50 */
"CSI1_DP1", /* GPIO_72, HSEC pin 48 */
"CSI1_CN", /* GPIO_73, HSEC pin 56 */
"CSI1_CP", /* GPIO_74, HSEC pin 54 */
"[CLK1]", /* GPIO_75, HSEC pin 17 */
"[GPIOD0]", /* GPIO_76 */
"[GPIOD1]", /* GPIO_77 */
"BT_RST_N", /* GPIO_78 */
"EXT_DC_EN", /* GPIO_79 */
"[PCM_DI]", /* GPIO_80, LSEC pin 22 */
"[PCM_DO]", /* GPIO_81, LSEC pin 20 */
"[PCM_CLK]", /* GPIO_82, LSEC pin 18 */
"[PCM_FS]", /* GPIO_83, LSEC pin 16 */
"WAKE_BT", /* GPIO_84 */
"WL_REG_ON", /* GPIO_85 */
"NC", /* GPIO_86 */
"NC", /* GPIO_87 */
"NC", /* GPIO_88 */
"NC", /* GPIO_89 */
"NC", /* GPIO_90 */
"WIFI_WAKE", /* GPIO_91 */
"BT_WAKE", /* GPIO_92 */
"NC", /* GPIO_93 */
"OTG_EN2", /* GPIO_94 */
"OTG_EN", /* GPIO_95 */
"DSI_DP3", /* GPIO_96, HSEC pin 45 */
"DSI_DN3", /* GPIO_97, HSEC pin 47 */
"DSI_DP1", /* GPIO_98, HSEC pin 33 */
"DSI_DN1", /* GPIO_99, HSEC pin 35 */
"DSI_CP", /* GPIO_100, HSEC pin 21 */
"DSI_CN", /* GPIO_101, HSEC pin 23 */
"DSI_DP0", /* GPIO_102, HSEC pin 27 */
"DSI_DN0", /* GPIO_103, HSEC pin 29 */
"DSI_DP2", /* GPIO_104, HSEC pin 39 */
"DSI_DN2", /* GPIO_105, HSEC pin 41 */
"N0_D0", /* GPIO_106 */
"N0_D1", /* GPIO_107 */
"N0_D2", /* GPIO_108 */
"N0_D3", /* GPIO_109 */
"N0_D4", /* GPIO_110 */
"N0_D5", /* GPIO_111 */
"N0_D6", /* GPIO_112 */
"N0_D7", /* GPIO_113 */
"N0_DQS", /* GPIO_114 */
"N0_DQSN", /* GPIO_115 */
"NC", /* GPIO_116 */
"NC", /* GPIO_117 */
"NC", /* GPIO_118 */
"N0_CEB1", /* GPIO_119 */
"CARD_DT", /* GPIO_120 */
"N0_CEB3", /* GPIO_121 */
"SD_DAT0", /* GPIO_122, HSEC pin 1 */
"SD_DAT1", /* GPIO_123, HSEC pin 3 */
"SD_DAT2", /* GPIO_124, HSEC pin 5 */
"SD_DAT3", /* GPIO_125, HSEC pin 7 */
"NC", /* GPIO_126 */
"NC", /* GPIO_127 */
"[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */
"[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */
"NC", /* GPIO_130 */
"SD_CMD", /* GPIO_131 */
"GPIO-L", /* GPIO_132, LSEC pin 34 */
"GPIO-K", /* GPIO_133, LSEC pin 33 */
"NC", /* GPIO_134 */
"SD_SCLK", /* GPIO_135 */
"NC", /* GPIO_136 */
"JTAG_TRST", /* GPIO_137 */
"I2C3_SCLK", /* GPIO_138 */
"LED2", /* GPIO_139 */
"LED3", /* GPIO_140 */
"I2C3_SDATA", /* GPIO_141 */
"UART3_RX", /* GPIO_142 */
"UART3_TX", /* GPIO_143 */
"UART3_RTSB", /* GPIO_144 */
"UART3_CTSB"; /* GPIO_145 */
i2c0_default: i2c0-default {
pinmux {
groups = "i2c0_mfp";
function = "i2c0";
};
pinconf {
pins = "i2c0_sclk", "i2c0_sdata";
bias-pull-up;
};
};
i2c1_default: i2c1-default {
pinconf {
pins = "i2c1_sclk", "i2c1_sdata";
bias-pull-up;
};
};
uart5_clk: uart5-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
i2c2_default: i2c2-default {
pinconf {
pins = "i2c2_sclk", "i2c2_sdata";
bias-pull-up;
};
};
};
......@@ -38,5 +249,4 @@ &timer {
&uart5 {
status = "okay";
clocks = <&uart5_clk>;
};
arch/arm64/boot/dts/actions/s900.dtsi
View file @ 6a11b180
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/actions,s900-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
......@@ -88,6 +88,18 @@ hosc: hosc {
#clock-cells = <0>;
};
losc: losc {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
diff24M: diff24M {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
......@@ -108,6 +120,7 @@ gic: interrupt-controller@e00f1000 {
uart0: serial@e0120000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0120000 0x0 0x2000>;
clocks = <&cmu CLK_UART0>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -115,6 +128,7 @@ uart0: serial@e0120000 {
uart1: serial@e0122000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0122000 0x0 0x2000>;
clocks = <&cmu CLK_UART1>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -122,6 +136,7 @@ uart1: serial@e0122000 {
uart2: serial@e0124000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0124000 0x0 0x2000>;
clocks = <&cmu CLK_UART2>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -129,6 +144,7 @@ uart2: serial@e0124000 {
uart3: serial@e0126000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
clocks = <&cmu CLK_UART3>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -136,6 +152,7 @@ uart3: serial@e0126000 {
uart4: serial@e0128000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0128000 0x0 0x2000>;
clocks = <&cmu CLK_UART4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -143,6 +160,7 @@ uart4: serial@e0128000 {
uart5: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
clocks = <&cmu CLK_UART5>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -150,15 +168,111 @@ uart5: serial@e012a000 {
uart6: serial@e012c000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012c000 0x0 0x2000>;
clocks = <&cmu CLK_UART6>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sps: power-controller@e012e000 {
compatible = "actions,s900-sps";
reg = <0x0 0xe012e000 0x0 0x2000>;
#power-domain-cells = <1>;
};
cmu: clock-controller@e0160000 {
compatible = "actions,s900-cmu";
reg = <0x0 0xe0160000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
};
i2c0: i2c@e0170000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0170000 0 0x1000>;
clocks = <&cmu CLK_I2C0>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e0172000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0172000 0 0x1000>;
clocks = <&cmu CLK_I2C1>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e0174000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0174000 0 0x1000>;
clocks = <&cmu CLK_I2C2>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e0176000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0176000 0 0x1000>;
clocks = <&cmu CLK_I2C3>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e0178000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0178000 0 0x1000>;
clocks = <&cmu CLK_I2C4>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e017a000 {
compatible = "actions,s900-i2c";
reg = <0 0xe017a000 0 0x1000>;
clocks = <&cmu CLK_I2C5>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 146>;
#gpio-cells = <2>;
};
timer: timer@e0228000 {
compatible = "actions,s900-timer";
reg = <0x0 0xe0228000 0x0 0x8000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "timer1";
};
dma: dma-controller@e0260000 {
compatible = "actions,s900-dma";
reg = <0x0 0xe0260000 0x0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <12>;
dma-requests = <46>;
clocks = <&cmu CLK_DMAC>;
};
};
};
include/dt-bindings/power/owl-s900-powergate.h 0 → 100644
View file @ 6a11b180
/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
/*
* Actions Semi S900 SPS
*
* Copyright (c) 2018 Linaro Ltd.
*/
#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
#define S900_PD_GPU_B 0
#define S900_PD_VCE 1
#define S900_PD_SENSOR 2
#define S900_PD_VDE 3
#define S900_PD_HDE 4
#define S900_PD_USB3 5
#define S900_PD_DDR0 6
#define S900_PD_DDR1 7
#define S900_PD_DE 8
#define S900_PD_NAND 9
#define S900_PD_USB2_H0 10
#define S900_PD_USB2_H1 11
#endif
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