Commit 6c34bc29 authored by Linus Torvalds's avatar Linus Torvalds

Revert "radeonfb: accelerate imageblit and other improvements"

This reverts commit b1ee26ba, along with
the "fixes" for it that all just caused problems:

 - c4c6fa98 "radeonfb: fix problem with
   color expansion & alignment"

 - f3179748 "radeonfb: Disable new color
   expand acceleration unless explicitely enabled"

because even when disabled, it breaks for people. See

	http://bugzilla.kernel.org/show_bug.cgi?id=12191

for the latest example.
Acked-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: default avatarDavid S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Cc: James Cloos <cloos@jhcloos.com>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Cc: Krzysztof Helt <krzysztof.h1@poczta.fm>
Cc: Jean-Luc Coulon <jean.luc.coulon@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 8b1fae4e
This diff is collapsed.
...@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd) ...@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
level = bd->props.brightness; level = bd->props.brightness;
del_timer_sync(&rinfo->lvds_timer); del_timer_sync(&rinfo->lvds_timer);
radeon_engine_idle(rinfo); radeon_engine_idle();
lvds_gen_cntl = INREG(LVDS_GEN_CNTL); lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
if (level > 0) { if (level > 0) {
......
...@@ -282,8 +282,6 @@ static int backlight = 1; ...@@ -282,8 +282,6 @@ static int backlight = 1;
static int backlight = 0; static int backlight = 0;
#endif #endif
int accel_cexp = 0;
/* /*
* prototypes * prototypes
*/ */
...@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var, ...@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
if (rinfo->asleep) if (rinfo->asleep)
return 0; return 0;
radeon_fifo_wait(2);
OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8) & ~7); * var->bits_per_pixel / 8) & ~7);
return 0; return 0;
...@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, ...@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
if (rc) if (rc)
return rc; return rc;
radeon_fifo_wait(2);
if (value & 0x01) { if (value & 0x01) {
tmp = INREG(LVDS_GEN_CNTL); tmp = INREG(LVDS_GEN_CNTL);
...@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) ...@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
if (rinfo->lock_blank) if (rinfo->lock_blank)
return 0; return 0;
radeon_engine_idle(rinfo); radeon_engine_idle();
val = INREG(CRTC_EXT_CNTL); val = INREG(CRTC_EXT_CNTL);
val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
...@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info) ...@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
if (rinfo->asleep) if (rinfo->asleep)
return 0; return 0;
return radeon_screen_blank(rinfo, blank, 0); return radeon_screen_blank(rinfo, blank, 0);
} }
...@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, ...@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
pindex = regno; pindex = regno;
if (!rinfo->asleep) { if (!rinfo->asleep) {
radeon_fifo_wait(9);
if (rinfo->bpp == 16) { if (rinfo->bpp == 16) {
pindex = regno * 8; pindex = regno * 8;
...@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg ...@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
{ {
int i; int i;
radeon_fifo_wait(20);
/* Workaround from XFree */ /* Workaround from XFree */
if (rinfo->is_mobility) { if (rinfo->is_mobility) {
/* A temporal workaround for the occational blanking on certain laptop /* A temporal workaround for the occational blanking on certain laptop
...@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data) ...@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
{ {
struct radeonfb_info *rinfo = (struct radeonfb_info *)data; struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
radeon_engine_idle(rinfo); radeon_engine_idle();
OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
} }
...@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, ...@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if (nomodeset) if (nomodeset)
return; return;
radeon_engine_idle(rinfo);
if (!regs_only) if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
radeon_fifo_wait(31);
for (i=0; i<10; i++) for (i=0; i<10; i++)
OUTREG(common_regs[i].reg, common_regs[i].val); OUTREG(common_regs[i].reg, common_regs[i].val);
...@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, ...@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
radeon_write_pll_regs(rinfo, mode); radeon_write_pll_regs(rinfo, mode);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
radeon_fifo_wait(10);
OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
...@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, ...@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if (!regs_only) if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
radeon_fifo_wait(2);
OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
return; return;
...@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info) ...@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
/* We always want engine to be idle on a mode switch, even /* We always want engine to be idle on a mode switch, even
* if we won't actually change the mode * if we won't actually change the mode
*/ */
radeon_engine_idle(rinfo); radeon_engine_idle();
hSyncStart = mode->xres + mode->right_margin; hSyncStart = mode->xres + mode->right_margin;
hSyncEnd = hSyncStart + mode->hsync_len; hSyncEnd = hSyncStart + mode->hsync_len;
...@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info) ...@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
return 0; return 0;
} }
static struct fb_ops radeonfb_ops = { static struct fb_ops radeonfb_ops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.fb_check_var = radeonfb_check_var, .fb_check_var = radeonfb_check_var,
...@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) ...@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->par = rinfo; info->par = rinfo;
info->pseudo_palette = rinfo->pseudo_palette; info->pseudo_palette = rinfo->pseudo_palette;
info->flags = FBINFO_DEFAULT info->flags = FBINFO_DEFAULT
| FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_XPAN
...@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) ...@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->fbops = &radeonfb_ops; info->fbops = &radeonfb_ops;
info->screen_base = rinfo->fb_base; info->screen_base = rinfo->fb_base;
info->screen_size = rinfo->mapped_vram; info->screen_size = rinfo->mapped_vram;
/* Fill fix common fields */ /* Fill fix common fields */
strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
info->fix.smem_start = rinfo->fb_base_phys; info->fix.smem_start = rinfo->fb_base_phys;
...@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo) ...@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->fix.mmio_len = RADEON_REGSIZE; info->fix.mmio_len = RADEON_REGSIZE;
info->fix.accel = FB_ACCEL_ATI_RADEON; info->fix.accel = FB_ACCEL_ATI_RADEON;
/* Allocate colormap */
fb_alloc_cmap(&info->cmap, 256, 0); fb_alloc_cmap(&info->cmap, 256, 0);
/* Setup pixmap used for acceleration */
#define PIXMAP_SIZE (2048 * 4)
info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
if (!info->pixmap.addr) {
printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
noaccel = 1;
goto bail;
}
info->pixmap.size = PIXMAP_SIZE;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
info->pixmap.scan_align = 4;
info->pixmap.buf_align = 4;
info->pixmap.access_align = 32;
bail:
if (noaccel) if (noaccel)
info->flags |= FBINFO_HWACCEL_DISABLED; info->flags |= FBINFO_HWACCEL_DISABLED;
...@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) ...@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
u32 tom = INREG(NB_TOM); u32 tom = INREG(NB_TOM);
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
radeon_fifo_wait(6);
OUTREG(MC_FB_LOCATION, tom); OUTREG(MC_FB_LOCATION, tom);
OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
...@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options) ...@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options)
} else if (!strncmp(this_opt, "ignore_devlist", 14)) { } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
ignore_devlist = 1; ignore_devlist = 1;
#endif #endif
} else if (!strncmp(this_opt, "accel_cexp", 12)) {
accel_cexp = 1;
} else } else
mode_option = this_opt; mode_option = this_opt;
} }
...@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0); ...@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0);
MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
module_param(force_measure_pll, bool, 0); module_param(force_measure_pll, bool, 0);
MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
module_param(accel_cexp, bool, 0);
MODULE_PARM_DESC(accel_cexp, "Use acceleration engine for color expansion");
#ifdef CONFIG_MTRR #ifdef CONFIG_MTRR
module_param(nomtrr, bool, 0); module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
......
...@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) ...@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
/* Make sure engine is reset */ /* Make sure engine is reset */
radeon_engine_idle(rinfo); radeon_engine_idle();
radeonfb_engine_reset(rinfo); radeonfb_engine_reset(rinfo);
radeon_engine_idle(rinfo); radeon_engine_idle();
} }
/* Blank display and LCD */ /* Blank display and LCD */
...@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev) ...@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
rinfo->asleep = 0; rinfo->asleep = 0;
} else } else
radeon_engine_idle(rinfo); radeon_engine_idle();
/* Restore display & engine */ /* Restore display & engine */
radeon_write_mode (rinfo, &rinfo->state, 1); radeon_write_mode (rinfo, &rinfo->state, 1);
......
...@@ -336,15 +336,7 @@ struct radeonfb_info { ...@@ -336,15 +336,7 @@ struct radeonfb_info {
int mon2_type; int mon2_type;
u8 *mon2_EDID; u8 *mon2_EDID;
/* accel bits */ u32 dp_gui_master_cntl;
u32 dp_gui_mc_base;
u32 dp_gui_mc_cache;
u32 dp_cntl_cache;
u32 dp_brush_fg_cache;
u32 dp_brush_bg_cache;
u32 dp_src_fg_cache;
u32 dp_src_bg_cache;
u32 fifo_free;
struct pll_info pll; struct pll_info pll;
...@@ -356,7 +348,6 @@ struct radeonfb_info { ...@@ -356,7 +348,6 @@ struct radeonfb_info {
int lock_blank; int lock_blank;
int dynclk; int dynclk;
int no_schedule; int no_schedule;
int gfx_mode;
enum radeon_pm_mode pm_mode; enum radeon_pm_mode pm_mode;
reinit_function_ptr reinit_func; reinit_function_ptr reinit_func;
...@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) ...@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr) readw((rinfo->mmio_base)+addr) #define INREG16(addr) readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
#ifdef CONFIG_PPC
#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
#else
#define INREG(addr) readl((rinfo->mmio_base)+addr) #define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
#endif
static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
u32 val, u32 mask) u32 val, u32 mask)
...@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth) ...@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
* 2D Engine helper routines * 2D Engine helper routines
*/ */
extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries); static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
int i;
for (i=0; i<2000000; i++) {
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}
static inline void radeon_engine_flush (struct radeonfb_info *rinfo) static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{ {
...@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) ...@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
/* Ensure FIFO is empty, ie, make sure the flush commands /* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache * has reached the cache
*/ */
radeon_fifo_update_and_wait(rinfo, 64); _radeon_fifo_wait (rinfo, 64);
/* Wait for the flush to complete */ /* Wait for the flush to complete */
for (i=0; i < 2000000; i++) { for (i=0; i < 2000000; i++) {
...@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) ...@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
} }
static inline void radeon_engine_idle(struct radeonfb_info *rinfo) static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{ {
int i; int i;
/* ensure FIFO is empty before waiting for idle */ /* ensure FIFO is empty before waiting for idle */
radeon_fifo_update_and_wait (rinfo, 64); _radeon_fifo_wait (rinfo, 64);
for (i=0; i<2000000; i++) { for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
...@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo) ...@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
} }
#define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
...@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image); ...@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
extern int radeonfb_sync(struct fb_info *info); extern int radeonfb_sync(struct fb_info *info);
extern void radeonfb_engine_init (struct radeonfb_info *rinfo); extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
/* Other functions */ /* Other functions */
extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
...@@ -638,6 +634,4 @@ static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {} ...@@ -638,6 +634,4 @@ static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {} static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
#endif #endif
extern int accel_cexp;
#endif /* __RADEONFB_H__ */ #endif /* __RADEONFB_H__ */
...@@ -525,9 +525,6 @@ ...@@ -525,9 +525,6 @@
#define CRTC_DISPLAY_DIS (1 << 10) #define CRTC_DISPLAY_DIS (1 << 10)
#define CRTC_CRT_ON (1 << 15) #define CRTC_CRT_ON (1 << 15)
/* DSTCACHE_MODE bits constants */
#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
/* DSTCACHE_CTLSTAT bit constants */ /* DSTCACHE_CTLSTAT bit constants */
#define RB2D_DC_FLUSH_2D (1 << 0) #define RB2D_DC_FLUSH_2D (1 << 0)
...@@ -869,10 +866,15 @@ ...@@ -869,10 +866,15 @@
#define GMC_DST_16BPP_YVYU422 0x00000c00 #define GMC_DST_16BPP_YVYU422 0x00000c00
#define GMC_DST_32BPP_AYUV444 0x00000e00 #define GMC_DST_32BPP_AYUV444 0x00000e00
#define GMC_DST_16BPP_ARGB4444 0x00000f00 #define GMC_DST_16BPP_ARGB4444 0x00000f00
#define GMC_SRC_MONO 0x00000000
#define GMC_SRC_MONO_LBKGD 0x00001000
#define GMC_SRC_DSTCOLOR 0x00003000
#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000
#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
#define GMC_DP_SRC_RECT 0x02000000
#define GMC_DP_SRC_HOST 0x03000000
#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
#define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_3D_FCN_EN_CLR 0x00000000
#define GMC_3D_FCN_EN_SET 0x08000000 #define GMC_3D_FCN_EN_SET 0x08000000
...@@ -883,9 +885,6 @@ ...@@ -883,9 +885,6 @@
#define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_LEAVE 0x00000000
#define GMC_WRITE_MASK_SET 0x40000000 #define GMC_WRITE_MASK_SET 0x40000000
#define GMC_CLR_CMP_CNTL_DIS (1 << 28) #define GMC_CLR_CMP_CNTL_DIS (1 << 28)
#define GMC_SRC_DATATYPE_MASK (3 << 12)
#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
#define GMC_SRC_DATATYPE_COLOR (3 << 12) #define GMC_SRC_DATATYPE_COLOR (3 << 12)
#define ROP3_S 0x00cc0000 #define ROP3_S 0x00cc0000
#define ROP3_SRCCOPY 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000
...@@ -894,7 +893,6 @@ ...@@ -894,7 +893,6 @@
#define DP_SRC_SOURCE_MASK (7 << 24) #define DP_SRC_SOURCE_MASK (7 << 24)
#define GMC_BRUSH_NONE (15 << 4) #define GMC_BRUSH_NONE (15 << 4)
#define DP_SRC_SOURCE_MEMORY (2 << 24) #define DP_SRC_SOURCE_MEMORY (2 << 24)
#define DP_SRC_SOURCE_HOST_DATA (3 << 24)
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
/* DP_MIX bit constants */ /* DP_MIX bit constants */
...@@ -980,12 +978,6 @@ ...@@ -980,12 +978,6 @@
#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
/* RBBM_GUICNTL constants */
#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0)
#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0)
/* masks */ /* masks */
#define CONFIG_MEMSIZE_MASK 0x1f000000 #define CONFIG_MEMSIZE_MASK 0x1f000000
......
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