Commit 6e9821b2 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gfx: minor code cleanup

Drop needless function wrapper.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cd75dc68
...@@ -3095,21 +3095,6 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) ...@@ -3095,21 +3095,6 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
return 0; return 0;
} }
/**
* gfx_v7_0_cp_compute_start - start the compute queues
*
* @adev: amdgpu_device pointer
*
* Enable the compute queues.
* Returns 0 for success, error for failure.
*/
static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev)
{
gfx_v7_0_cp_compute_enable(adev, true);
return 0;
}
/** /**
* gfx_v7_0_cp_compute_fini - stop the compute queues * gfx_v7_0_cp_compute_fini - stop the compute queues
* *
...@@ -3300,9 +3285,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) ...@@ -3300,9 +3285,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
u32 *buf; u32 *buf;
struct bonaire_mqd *mqd; struct bonaire_mqd *mqd;
r = gfx_v7_0_cp_compute_start(adev); gfx_v7_0_cp_compute_enable(adev, true);
if (r)
return r;
/* fix up chicken bits */ /* fix up chicken bits */
tmp = RREG32(mmCP_CPF_DEBUG); tmp = RREG32(mmCP_CPF_DEBUG);
......
...@@ -3226,13 +3226,6 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) ...@@ -3226,13 +3226,6 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
udelay(50); udelay(50);
} }
static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
{
gfx_v8_0_cp_compute_enable(adev, true);
return 0;
}
static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
{ {
const struct gfx_firmware_header_v1_0 *mec_hdr; const struct gfx_firmware_header_v1_0 *mec_hdr;
...@@ -3802,9 +3795,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) ...@@ -3802,9 +3795,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
WREG32(mmCP_PQ_STATUS, tmp); WREG32(mmCP_PQ_STATUS, tmp);
} }
r = gfx_v8_0_cp_compute_start(adev); gfx_v8_0_cp_compute_enable(adev, true);
if (r)
return r;
for (i = 0; i < adev->gfx.num_compute_rings; i++) { for (i = 0; i < adev->gfx.num_compute_rings; i++) {
struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
......
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