drm/amd/display: prep work for root clock optimization enablement for DCN314
To enable root clock optimizations, we need a number of register writes and need to account for the difference in DPSTREAMCLK between DCN31 and DCN314. To prevent issues, add a number of register writes to DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init() which is mostly in alignment with dccg31_init() but accounts for the new DPSTREAMCLK sequence. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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