Commit 70aa8670 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/disp: convert to new-style nvkm_engine

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent bd70563f
...@@ -5,8 +5,8 @@ ...@@ -5,8 +5,8 @@
#include <core/event.h> #include <core/event.h>
struct nvkm_disp { struct nvkm_disp {
struct nvkm_engine engine;
const struct nvkm_disp_func *func; const struct nvkm_disp_func *func;
struct nvkm_engine engine;
struct nvkm_oproxy *client; struct nvkm_oproxy *client;
...@@ -15,21 +15,21 @@ struct nvkm_disp { ...@@ -15,21 +15,21 @@ struct nvkm_disp {
struct nvkm_event hpd; struct nvkm_event hpd;
struct nvkm_event vblank; struct nvkm_event vblank;
};
struct nvkm_disp_func { struct {
const struct nvkm_disp_oclass *root; int nr;
} head;
}; };
extern struct nvkm_oclass *nv04_disp_oclass; int nv04_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *nv50_disp_oclass; int nv50_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *g84_disp_oclass; int g84_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gt200_disp_oclass; int gt200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *g94_disp_oclass; int g94_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gt215_disp_oclass; int gt215_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gf110_disp_oclass; int gf119_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gk104_disp_oclass; int gk104_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gk110_disp_oclass; int gk110_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gm107_disp_oclass; int gm107_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
extern struct nvkm_oclass *gm204_disp_oclass; int gm204_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
#endif #endif
...@@ -31,63 +31,54 @@ gf100_identify(struct nvkm_device *device) ...@@ -31,63 +31,54 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xc4: case 0xc4:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xc3: case 0xc3:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xce: case 0xce:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xcf: case 0xcf:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xc1: case 0xc1:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break; break;
case 0xc8: case 0xc8:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break; break;
case 0xd9: case 0xd9:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break; break;
case 0xd7: case 0xd7:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break; break;
default: default:
......
...@@ -31,21 +31,18 @@ gk104_identify(struct nvkm_device *device) ...@@ -31,21 +31,18 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break; break;
case 0xe7: case 0xe7:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break; break;
case 0xe6: case 0xe6:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break; break;
case 0xea: case 0xea:
...@@ -58,27 +55,23 @@ gk104_identify(struct nvkm_device *device) ...@@ -58,27 +55,23 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break; break;
case 0xf1: case 0xf1:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break; break;
case 0x106: case 0x106:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
break; break;
case 0x108: case 0x108:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -34,7 +34,6 @@ gm100_identify(struct nvkm_device *device) ...@@ -34,7 +34,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
#if 0 #if 0
#endif #endif
#if 0 #if 0
...@@ -50,7 +49,6 @@ gm100_identify(struct nvkm_device *device) ...@@ -50,7 +49,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0 #if 0
#endif #endif
break; break;
...@@ -64,7 +62,6 @@ gm100_identify(struct nvkm_device *device) ...@@ -64,7 +62,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0 #if 0
#endif #endif
break; break;
......
...@@ -31,13 +31,11 @@ nv04_identify(struct nvkm_device *device) ...@@ -31,13 +31,11 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x05: case 0x05:
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -29,49 +29,41 @@ nv10_identify(struct nvkm_device *device) ...@@ -29,49 +29,41 @@ nv10_identify(struct nvkm_device *device)
switch (device->chipset) { switch (device->chipset) {
case 0x10: case 0x10:
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x15: case 0x15:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x16: case 0x16:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x1a: case 0x1a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x11: case 0x11:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x17: case 0x17:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x1f: case 0x1f:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x18: case 0x18:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -31,25 +31,21 @@ nv20_identify(struct nvkm_device *device) ...@@ -31,25 +31,21 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x25: case 0x25:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x28: case 0x28:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x2a: case 0x2a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -31,34 +31,29 @@ nv30_identify(struct nvkm_device *device) ...@@ -31,34 +31,29 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x35: case 0x35:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x31: case 0x31:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x36: case 0x36:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x34: case 0x34:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -32,7 +32,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -32,7 +32,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x41: case 0x41:
...@@ -40,7 +39,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -40,7 +39,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x42: case 0x42:
...@@ -48,7 +46,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -48,7 +46,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x43: case 0x43:
...@@ -56,7 +53,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -56,7 +53,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x45: case 0x45:
...@@ -64,7 +60,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -64,7 +60,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x47: case 0x47:
...@@ -72,7 +67,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -72,7 +67,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x49: case 0x49:
...@@ -80,7 +74,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -80,7 +74,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x4b: case 0x4b:
...@@ -88,7 +81,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -88,7 +81,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x44: case 0x44:
...@@ -96,7 +88,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -96,7 +88,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x46: case 0x46:
...@@ -104,7 +95,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -104,7 +95,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x4a: case 0x4a:
...@@ -112,7 +102,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -112,7 +102,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x4c: case 0x4c:
...@@ -120,7 +109,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -120,7 +109,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x4e: case 0x4e:
...@@ -128,7 +116,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -128,7 +116,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x63: case 0x63:
...@@ -136,7 +123,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -136,7 +123,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x67: case 0x67:
...@@ -144,7 +130,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -144,7 +130,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
case 0x68: case 0x68:
...@@ -152,7 +137,6 @@ nv40_identify(struct nvkm_device *device) ...@@ -152,7 +137,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break; break;
default: default:
......
...@@ -32,7 +32,6 @@ nv50_identify(struct nvkm_device *device) ...@@ -32,7 +32,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break; break;
case 0x84: case 0x84:
...@@ -40,7 +39,6 @@ nv50_identify(struct nvkm_device *device) ...@@ -40,7 +39,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0x86: case 0x86:
...@@ -48,7 +46,6 @@ nv50_identify(struct nvkm_device *device) ...@@ -48,7 +46,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0x92: case 0x92:
...@@ -56,7 +53,6 @@ nv50_identify(struct nvkm_device *device) ...@@ -56,7 +53,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0x94: case 0x94:
...@@ -64,7 +60,6 @@ nv50_identify(struct nvkm_device *device) ...@@ -64,7 +60,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0x96: case 0x96:
...@@ -72,14 +67,12 @@ nv50_identify(struct nvkm_device *device) ...@@ -72,14 +67,12 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0x98: case 0x98:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0xa0: case 0xa0:
...@@ -87,21 +80,18 @@ nv50_identify(struct nvkm_device *device) ...@@ -87,21 +80,18 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break; break;
case 0xaa: case 0xaa:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0xac: case 0xac:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break; break;
case 0xa3: case 0xa3:
...@@ -109,28 +99,24 @@ nv50_identify(struct nvkm_device *device) ...@@ -109,28 +99,24 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break; break;
case 0xa5: case 0xa5:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break; break;
case 0xa8: case 0xa8:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break; break;
case 0xaf: case 0xaf:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break; break;
default: default:
......
...@@ -35,7 +35,21 @@ ...@@ -35,7 +35,21 @@
#include <nvif/event.h> #include <nvif/event.h>
#include <nvif/unpack.h> #include <nvif/unpack.h>
int static void
nvkm_disp_vblank_fini(struct nvkm_event *event, int type, int head)
{
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
disp->func->head.vblank_fini(disp, head);
}
static void
nvkm_disp_vblank_init(struct nvkm_event *event, int type, int head)
{
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
disp->func->head.vblank_init(disp, head);
}
static int
nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size, nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify) struct nvkm_notify *notify)
{ {
...@@ -58,6 +72,13 @@ nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size, ...@@ -58,6 +72,13 @@ nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size,
return ret; return ret;
} }
static const struct nvkm_event_func
nvkm_disp_vblank_func = {
.ctor = nvkm_disp_vblank_ctor,
.init = nvkm_disp_vblank_init,
.fini = nvkm_disp_vblank_fini,
};
void void
nvkm_disp_vblank(struct nvkm_disp *disp, int head) nvkm_disp_vblank(struct nvkm_disp *disp, int head)
{ {
...@@ -102,7 +123,7 @@ nvkm_disp_hpd_func = { ...@@ -102,7 +123,7 @@ nvkm_disp_hpd_func = {
int int
nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event) nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event)
{ {
struct nvkm_disp *disp = (void *)object->engine; struct nvkm_disp *disp = nvkm_disp(object->engine);
switch (type) { switch (type) {
case NV04_DISP_NTFY_VBLANK: case NV04_DISP_NTFY_VBLANK:
*event = &disp->vblank; *event = &disp->vblank;
...@@ -168,18 +189,26 @@ nvkm_disp_class_get(struct nvkm_oclass *oclass, int index, ...@@ -168,18 +189,26 @@ nvkm_disp_class_get(struct nvkm_oclass *oclass, int index,
{ {
struct nvkm_disp *disp = nvkm_disp(oclass->engine); struct nvkm_disp *disp = nvkm_disp(oclass->engine);
if (index == 0) { if (index == 0) {
oclass->base = disp->func->root->base; const struct nvkm_disp_oclass *root = disp->func->root(disp);
oclass->engn = disp->func->root; oclass->base = root->base;
oclass->engn = root;
*class = &nvkm_disp_sclass; *class = &nvkm_disp_sclass;
return 0; return 0;
} }
return 1; return 1;
} }
int static void
_nvkm_disp_fini(struct nvkm_object *object, bool suspend) nvkm_disp_intr(struct nvkm_engine *engine)
{
struct nvkm_disp *disp = nvkm_disp(engine);
disp->func->intr(disp);
}
static int
nvkm_disp_fini(struct nvkm_engine *engine, bool suspend)
{ {
struct nvkm_disp *disp = (void *)object; struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn; struct nvkm_connector *conn;
struct nvkm_output *outp; struct nvkm_output *outp;
...@@ -191,20 +220,15 @@ _nvkm_disp_fini(struct nvkm_object *object, bool suspend) ...@@ -191,20 +220,15 @@ _nvkm_disp_fini(struct nvkm_object *object, bool suspend)
nvkm_connector_fini(conn); nvkm_connector_fini(conn);
} }
return nvkm_engine_fini_old(&disp->engine, suspend); return 0;
} }
int static int
_nvkm_disp_init(struct nvkm_object *object) nvkm_disp_init(struct nvkm_engine *engine)
{ {
struct nvkm_disp *disp = (void *)object; struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn; struct nvkm_connector *conn;
struct nvkm_output *outp; struct nvkm_output *outp;
int ret;
ret = nvkm_engine_init_old(&disp->engine);
if (ret)
return ret;
list_for_each_entry(conn, &disp->conn, head) { list_for_each_entry(conn, &disp->conn, head) {
nvkm_connector_init(conn); nvkm_connector_init(conn);
...@@ -214,15 +238,19 @@ _nvkm_disp_init(struct nvkm_object *object) ...@@ -214,15 +238,19 @@ _nvkm_disp_init(struct nvkm_object *object)
nvkm_output_init(outp); nvkm_output_init(outp);
} }
return ret; return 0;
} }
void static void *
_nvkm_disp_dtor(struct nvkm_object *object) nvkm_disp_dtor(struct nvkm_engine *engine)
{ {
struct nvkm_disp *disp = (void *)object; struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn; struct nvkm_connector *conn;
struct nvkm_output *outp; struct nvkm_output *outp;
void *data = disp;
if (disp->func->dtor)
data = disp->func->dtor(disp);
nvkm_event_fini(&disp->vblank); nvkm_event_fini(&disp->vblank);
nvkm_event_fini(&disp->hpd); nvkm_event_fini(&disp->hpd);
...@@ -239,40 +267,40 @@ _nvkm_disp_dtor(struct nvkm_object *object) ...@@ -239,40 +267,40 @@ _nvkm_disp_dtor(struct nvkm_object *object)
nvkm_connector_del(&conn); nvkm_connector_del(&conn);
} }
nvkm_engine_destroy(&disp->engine); return data;
} }
static const struct nvkm_engine_func static const struct nvkm_engine_func
nvkm_disp = { nvkm_disp = {
.dtor = nvkm_disp_dtor,
.init = nvkm_disp_init,
.fini = nvkm_disp_fini,
.intr = nvkm_disp_intr,
.base.sclass = nvkm_disp_class_get, .base.sclass = nvkm_disp_class_get,
}; };
int int
nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device,
struct nvkm_oclass *oclass, int heads, const char *intname, int index, int heads, struct nvkm_disp *disp)
const char *extname, int length, void **pobject)
{ {
struct nvkm_disp_impl *impl = (void *)oclass;
struct nvkm_device *device = (void *)parent;
struct nvkm_bios *bios = device->bios; struct nvkm_bios *bios = device->bios;
struct nvkm_disp *disp;
struct nvkm_connector *conn;
struct nvkm_output *outp, *outt, *pair; struct nvkm_output *outp, *outt, *pair;
struct nvkm_connector *conn;
struct nvbios_connE connE; struct nvbios_connE connE;
struct dcb_output dcbE; struct dcb_output dcbE;
u8 hpd = 0, ver, hdr; u8 hpd = 0, ver, hdr;
u32 data; u32 data;
int ret, i; int ret, i;
ret = nvkm_engine_create_(parent, engine, oclass, true, intname,
extname, length, pobject);
disp = *pobject;
if (ret)
return ret;
disp->engine.func = &nvkm_disp;
INIT_LIST_HEAD(&disp->outp); INIT_LIST_HEAD(&disp->outp);
INIT_LIST_HEAD(&disp->conn); INIT_LIST_HEAD(&disp->conn);
disp->func = func;
disp->head.nr = heads;
ret = nvkm_engine_ctor(&nvkm_disp, device, index, 0,
true, &disp->engine);
if (ret)
return ret;
/* create output objects for each display path in the vbios */ /* create output objects for each display path in the vbios */
i = -1; i = -1;
...@@ -288,8 +316,8 @@ nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -288,8 +316,8 @@ nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine,
outp = NULL; outp = NULL;
switch (dcbE.location) { switch (dcbE.location) {
case 0: outps = &impl->outp.internal; break; case 0: outps = &disp->func->outp.internal; break;
case 1: outps = &impl->outp.external; break; case 1: outps = &disp->func->outp.external; break;
default: default:
nvkm_warn(&disp->engine.subdev, nvkm_warn(&disp->engine.subdev,
"dcb %d locn %d unknown\n", i, dcbE.location); "dcb %d locn %d unknown\n", i, dcbE.location);
...@@ -394,9 +422,18 @@ nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -394,9 +422,18 @@ nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine,
if (ret) if (ret)
return ret; return ret;
ret = nvkm_event_init(impl->vblank, 1, heads, &disp->vblank); ret = nvkm_event_init(&nvkm_disp_vblank_func, 1, heads, &disp->vblank);
if (ret) if (ret)
return ret; return ret;
return 0; return 0;
} }
int
nvkm_disp_new_(const struct nvkm_disp_func *func, struct nvkm_device *device,
int index, int heads, struct nvkm_disp **pdisp)
{
if (!(*pdisp = kzalloc(sizeof(**pdisp), GFP_KERNEL)))
return -ENOMEM;
return nvkm_disp_ctor(func, device, index, heads, *pdisp);
}
...@@ -49,7 +49,7 @@ nv50_disp_base_new(const struct nv50_disp_dmac_func *func, ...@@ -49,7 +49,7 @@ nv50_disp_base_new(const struct nv50_disp_dmac_func *func,
nvif_ioctl(parent, "create disp base channel dma vers %d " nvif_ioctl(parent, "create disp base channel dma vers %d "
"pushbuf %016llx head %d\n", "pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head); args->v0.version, args->v0.pushbuf, args->v0.head);
if (args->v0.head > disp->head.nr) if (args->v0.head > disp->base.head.nr)
return -EINVAL; return -EINVAL;
push = args->v0.pushbuf; push = args->v0.pushbuf;
head = args->v0.head; head = args->v0.head;
......
...@@ -47,7 +47,7 @@ nv50_disp_curs_new(const struct nv50_disp_chan_func *func, ...@@ -47,7 +47,7 @@ nv50_disp_curs_new(const struct nv50_disp_chan_func *func,
if (nvif_unpack(args->v0, 0, 0, false)) { if (nvif_unpack(args->v0, 0, 0, false)) {
nvif_ioctl(parent, "create disp cursor vers %d head %d\n", nvif_ioctl(parent, "create disp cursor vers %d head %d\n",
args->v0.version, args->v0.head); args->v0.version, args->v0.head);
if (args->v0.head > disp->head.nr) if (args->v0.head > disp->base.head.nr)
return -EINVAL; return -EINVAL;
head = args->v0.head; head = args->v0.head;
} else } else
......
...@@ -322,7 +322,7 @@ void ...@@ -322,7 +322,7 @@ void
nvkm_dp_train(struct work_struct *w) nvkm_dp_train(struct work_struct *w)
{ {
struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
struct nv50_disp *disp = (void *)outp->base.disp; struct nv50_disp *disp = nv50_disp(outp->base.disp);
const struct dp_rates *cfg = nvkm_dp_rates; const struct dp_rates *cfg = nvkm_dp_rates;
struct dp_state _dp = { struct dp_state _dp = {
.outp = outp, .outp = outp,
...@@ -330,8 +330,8 @@ nvkm_dp_train(struct work_struct *w) ...@@ -330,8 +330,8 @@ nvkm_dp_train(struct work_struct *w)
u32 datarate = 0; u32 datarate = 0;
int ret; int ret;
if (!outp->base.info.location && disp->sor.magic) if (!outp->base.info.location && disp->func->sor.magic)
disp->sor.magic(&outp->base); disp->func->sor.magic(&outp->base);
/* bring capabilities within encoder limits */ /* bring capabilities within encoder limits */
if (disp->base.engine.subdev.device->chipset < 0xd0) if (disp->base.engine.subdev.device->chipset < 0xd0)
......
...@@ -24,59 +24,32 @@ ...@@ -24,59 +24,32 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
g84_disp = { g84_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &g84_disp_root_oclass, .root = &g84_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_disp_vblank_fini,
.head.scanoutpos = nv50_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 2,
.sor.power = nv50_sor_power,
.sor.hdmi = g84_hdmi_ctrl,
.pior.nr = 3,
.pior.power = nv50_pior_power,
}; };
static int int
g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nv50_disp *disp; return nv50_disp_new_(&g84_disp, device, index, 2, pdisp);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &g84_disp;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 2;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
} }
struct nvkm_oclass *
g84_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x82),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g84_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.external.tmds = nv50_pior_output_new,
.base.outp.external.dp = nv50_pior_dp_new,
.base.vblank = &nv50_disp_vblank_func,
.head.scanoutpos = nv50_disp_root_scanoutpos,
}.base.base;
...@@ -24,60 +24,33 @@ ...@@ -24,60 +24,33 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
g94_disp = { g94_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &g94_disp_root_oclass, .root = &g94_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_disp_vblank_fini,
.head.scanoutpos = nv50_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hdmi = g84_hdmi_ctrl,
.pior.nr = 3,
.pior.power = nv50_pior_power,
}; };
static int int
g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g94_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nv50_disp *disp; return nv50_disp_new_(&g94_disp, device, index, 2, pdisp);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &g94_disp;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
} }
struct nvkm_oclass *
g94_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x88),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g94_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = g94_sor_dp_new,
.base.outp.external.lvds = nv50_pior_output_new,
.base.outp.external.dp = nv50_pior_dp_new,
.base.vblank = &nv50_disp_vblank_func,
.head.scanoutpos = nv50_disp_root_scanoutpos,
}.base.base;
...@@ -30,29 +30,20 @@ ...@@ -30,29 +30,20 @@
#include <subdev/bios/pll.h> #include <subdev/bios/pll.h>
#include <subdev/devinit.h> #include <subdev/devinit.h>
static void void
gf119_disp_vblank_init(struct nvkm_event *event, int type, int head) gf119_disp_vblank_init(struct nv50_disp *disp, int head)
{ {
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
} }
static void void
gf119_disp_vblank_fini(struct nvkm_event *event, int type, int head) gf119_disp_vblank_fini(struct nv50_disp *disp, int head)
{ {
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
} }
const struct nvkm_event_func
gf119_disp_vblank_func = {
.ctor = nvkm_disp_vblank_ctor,
.init = gf119_disp_vblank_init,
.fini = gf119_disp_vblank_fini,
};
static struct nvkm_output * static struct nvkm_output *
exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
...@@ -103,7 +94,8 @@ exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, ...@@ -103,7 +94,8 @@ exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
static struct nvkm_output * static struct nvkm_output *
exec_script(struct nv50_disp *disp, int head, int id) exec_script(struct nv50_disp *disp, int head, int id)
{ {
struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios; struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp; struct nvkm_output *outp;
struct nvbios_outp info; struct nvbios_outp info;
...@@ -123,7 +115,7 @@ exec_script(struct nv50_disp *disp, int head, int id) ...@@ -123,7 +115,7 @@ exec_script(struct nv50_disp *disp, int head, int id)
outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
if (outp) { if (outp) {
struct nvbios_init init = { struct nvbios_init init = {
.subdev = nv_subdev(disp), .subdev = subdev,
.bios = bios, .bios = bios,
.offset = info.script[id], .offset = info.script[id],
.outp = &outp->info, .outp = &outp->info,
...@@ -140,7 +132,8 @@ exec_script(struct nv50_disp *disp, int head, int id) ...@@ -140,7 +132,8 @@ exec_script(struct nv50_disp *disp, int head, int id)
static struct nvkm_output * static struct nvkm_output *
exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
{ {
struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios; struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp; struct nvkm_output *outp;
struct nvbios_outp info1; struct nvbios_outp info1;
...@@ -185,7 +178,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) ...@@ -185,7 +178,7 @@ exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
if (data) { if (data) {
struct nvbios_init init = { struct nvbios_init init = {
.subdev = nv_subdev(disp), .subdev = subdev,
.bios = bios, .bios = bios,
.offset = data, .offset = data,
.outp = &outp->info, .outp = &outp->info,
...@@ -329,8 +322,8 @@ gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head) ...@@ -329,8 +322,8 @@ gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head)
if (nvkm_output_dp_train(outp, pclk, true)) if (nvkm_output_dp_train(outp, pclk, true))
OUTP_ERR(outp, "link not trained before attach"); OUTP_ERR(outp, "link not trained before attach");
} else { } else {
if (disp->sor.magic) if (disp->func->sor.magic)
disp->sor.magic(outp); disp->func->sor.magic(outp);
} }
exec_clkcmp(disp, head, 0, pclk, &conf); exec_clkcmp(disp, head, 0, pclk, &conf);
...@@ -377,14 +370,14 @@ gf119_disp_intr_supervisor(struct work_struct *work) ...@@ -377,14 +370,14 @@ gf119_disp_intr_supervisor(struct work_struct *work)
int head; int head;
nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super)); nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800)); mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800));
nvkm_debug(subdev, "head %d: %08x\n", head, mask[head]); nvkm_debug(subdev, "head %d: %08x\n", head, mask[head]);
} }
if (disp->super & 0x00000001) { if (disp->super & 0x00000001) {
nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000)) if (!(mask[head] & 0x00001000))
continue; continue;
nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head); nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head);
...@@ -392,19 +385,19 @@ gf119_disp_intr_supervisor(struct work_struct *work) ...@@ -392,19 +385,19 @@ gf119_disp_intr_supervisor(struct work_struct *work)
} }
} else } else
if (disp->super & 0x00000002) { if (disp->super & 0x00000002) {
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000)) if (!(mask[head] & 0x00001000))
continue; continue;
nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head); nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head);
gf119_disp_intr_unk2_0(disp, head); gf119_disp_intr_unk2_0(disp, head);
} }
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00010000)) if (!(mask[head] & 0x00010000))
continue; continue;
nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head); nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head);
gf119_disp_intr_unk2_1(disp, head); gf119_disp_intr_unk2_1(disp, head);
} }
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000)) if (!(mask[head] & 0x00001000))
continue; continue;
nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head); nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head);
...@@ -412,7 +405,7 @@ gf119_disp_intr_supervisor(struct work_struct *work) ...@@ -412,7 +405,7 @@ gf119_disp_intr_supervisor(struct work_struct *work)
} }
} else } else
if (disp->super & 0x00000004) { if (disp->super & 0x00000004) {
for (head = 0; head < disp->head.nr; head++) { for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000)) if (!(mask[head] & 0x00001000))
continue; continue;
nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head); nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head);
...@@ -420,7 +413,7 @@ gf119_disp_intr_supervisor(struct work_struct *work) ...@@ -420,7 +413,7 @@ gf119_disp_intr_supervisor(struct work_struct *work)
} }
} }
for (head = 0; head < disp->head.nr; head++) for (head = 0; head < disp->base.head.nr; head++)
nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000); nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000);
nvkm_wr32(device, 0x6101d0, 0x80000000); nvkm_wr32(device, 0x6101d0, 0x80000000);
} }
...@@ -452,9 +445,9 @@ gf119_disp_intr_error(struct nv50_disp *disp, int chid) ...@@ -452,9 +445,9 @@ gf119_disp_intr_error(struct nv50_disp *disp, int chid)
} }
void void
gf119_disp_intr(struct nvkm_subdev *subdev) gf119_disp_intr(struct nv50_disp *disp)
{ {
struct nv50_disp *disp = (void *)subdev; struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device; struct nvkm_device *device = subdev->device;
u32 intr = nvkm_rd32(device, 0x610088); u32 intr = nvkm_rd32(device, 0x610088);
int i; int i;
...@@ -494,7 +487,7 @@ gf119_disp_intr(struct nvkm_subdev *subdev) ...@@ -494,7 +487,7 @@ gf119_disp_intr(struct nvkm_subdev *subdev)
intr &= ~0x00100000; intr &= ~0x00100000;
} }
for (i = 0; i < disp->head.nr; i++) { for (i = 0; i < disp->base.head.nr; i++) {
u32 mask = 0x01000000 << i; u32 mask = 0x01000000 << i;
if (mask & intr) { if (mask & intr) {
u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800)); u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800));
...@@ -506,59 +499,38 @@ gf119_disp_intr(struct nvkm_subdev *subdev) ...@@ -506,59 +499,38 @@ gf119_disp_intr(struct nvkm_subdev *subdev)
} }
} }
static const struct nvkm_disp_func int
gf119_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
int index, struct nvkm_disp **pdisp)
{
u32 heads = nvkm_rd32(device, 0x022448);
return nv50_disp_new_(func, device, index, heads, pdisp);
}
static const struct nv50_disp_func
gf119_disp = { gf119_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gf119_disp_root_oclass, .root = &gf119_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini = gf119_disp_vblank_fini,
.head.scanoutpos = gf119_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gf119_hda_eld,
.sor.hdmi = gf119_hdmi_ctrl,
}; };
static int int
gf119_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; return gf119_disp_new_(&gf119_disp, device, index, pdisp);
struct nv50_disp *disp;
int heads = nvkm_rd32(device, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gf119_disp;
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = gf119_disp_intr;
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf119_hda_eld;
disp->sor.hdmi = gf119_hdmi_ctrl;
return 0;
} }
struct nvkm_oclass *
gf110_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x90),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf119_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = gf119_sor_dp_new,
.base.vblank = &gf119_disp_vblank_func,
.head.scanoutpos = gf119_disp_root_scanoutpos,
}.base.base;
...@@ -24,59 +24,30 @@ ...@@ -24,59 +24,30 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gk104_disp = { gk104_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gk104_disp_root_oclass, .root = &gk104_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini = gf119_disp_vblank_fini,
.head.scanoutpos = gf119_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gf119_hda_eld,
.sor.hdmi = gk104_hdmi_ctrl,
}; };
static int int
gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; return gf119_disp_new_(&gk104_disp, device, index, pdisp);
struct nv50_disp *disp;
int heads = nvkm_rd32(device, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gk104_disp;
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = gf119_disp_intr;
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf119_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
} }
struct nvkm_oclass *
gk104_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x91),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk104_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = gf119_sor_dp_new,
.base.vblank = &gf119_disp_vblank_func,
.head.scanoutpos = gf119_disp_root_scanoutpos,
}.base.base;
...@@ -24,59 +24,30 @@ ...@@ -24,59 +24,30 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gk110_disp = { gk110_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gk110_disp_root_oclass, .root = &gk110_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini = gf119_disp_vblank_fini,
.head.scanoutpos = gf119_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gf119_hda_eld,
.sor.hdmi = gk104_hdmi_ctrl,
}; };
static int int
gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk110_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; return gf119_disp_new_(&gk110_disp, device, index, pdisp);
struct nv50_disp *disp;
int heads = nvkm_rd32(device, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gk110_disp;
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = gf119_disp_intr;
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf119_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
} }
struct nvkm_oclass *
gk110_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x92),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk110_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = gf119_sor_dp_new,
.base.vblank = &gf119_disp_vblank_func,
.head.scanoutpos = gf119_disp_root_scanoutpos,
}.base.base;
...@@ -24,59 +24,30 @@ ...@@ -24,59 +24,30 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gm107_disp = { gm107_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gm107_disp_root_oclass, .root = &gm107_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini = gf119_disp_vblank_fini,
.head.scanoutpos = gf119_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gf119_hda_eld,
.sor.hdmi = gk104_hdmi_ctrl,
}; };
static int int
gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm107_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; return gf119_disp_new_(&gm107_disp, device, index, pdisp);
struct nv50_disp *disp;
int heads = nvkm_rd32(device, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gm107_disp;
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = gf119_disp_intr;
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf119_hda_eld;
disp->sor.hdmi = gk104_hdmi_ctrl;
return 0;
} }
struct nvkm_oclass *
gm107_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x07),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm107_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = gf119_sor_dp_new,
.base.vblank = &gf119_disp_vblank_func,
.head.scanoutpos = gf119_disp_root_scanoutpos,
}.base.base;
...@@ -24,60 +24,31 @@ ...@@ -24,60 +24,31 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gm204_disp = { gm204_disp = {
.intr = gf119_disp_intr,
.uevent = &gf119_disp_chan_uevent,
.super = gf119_disp_intr_supervisor,
.root = &gm204_disp_root_oclass, .root = &gm204_disp_root_oclass,
.head.vblank_init = gf119_disp_vblank_init,
.head.vblank_fini = gf119_disp_vblank_fini,
.head.scanoutpos = gf119_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gm204_sor_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gf119_hda_eld,
.sor.hdmi = gk104_hdmi_ctrl,
.sor.magic = gm204_sor_magic,
}; };
static int int
gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_device *device = (void *)parent; return gf119_disp_new_(&gm204_disp, device, index, pdisp);
struct nv50_disp *disp;
int heads = nvkm_rd32(device, 0x022448);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, heads,
"PDISP", "display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gm204_disp;
ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = gf119_disp_intr;
INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
disp->head.nr = heads;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gf119_hda_eld;
disp->sor.hdmi = gf119_hdmi_ctrl;
disp->sor.magic = gm204_sor_magic;
return 0;
} }
struct nvkm_oclass *
gm204_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x07),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = gm204_sor_dp_new,
.base.vblank = &gf119_disp_vblank_func,
.head.scanoutpos = gf119_disp_root_scanoutpos,
}.base.base;
...@@ -24,59 +24,32 @@ ...@@ -24,59 +24,32 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gt200_disp = { gt200_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &gt200_disp_root_oclass, .root = &gt200_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_disp_vblank_fini,
.head.scanoutpos = nv50_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 2,
.sor.power = nv50_sor_power,
.sor.hdmi = g84_hdmi_ctrl,
.pior.nr = 3,
.pior.power = nv50_pior_power,
}; };
static int int
gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nv50_disp *disp; return nv50_disp_new_(&gt200_disp, device, index, 2, pdisp);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gt200_disp;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 2;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hdmi = g84_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
} }
struct nvkm_oclass *
gt200_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x83),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gt200_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.external.tmds = nv50_pior_output_new,
.base.outp.external.dp = nv50_pior_dp_new,
.base.vblank = &nv50_disp_vblank_func,
.head.scanoutpos = nv50_disp_root_scanoutpos,
}.base.base;
...@@ -24,61 +24,34 @@ ...@@ -24,61 +24,34 @@
#include "nv50.h" #include "nv50.h"
#include "rootnv50.h" #include "rootnv50.h"
static const struct nvkm_disp_func static const struct nv50_disp_func
gt215_disp_func = { gt215_disp = {
.intr = nv50_disp_intr,
.uevent = &nv50_disp_chan_uevent,
.super = nv50_disp_intr_supervisor,
.root = &gt215_disp_root_oclass, .root = &gt215_disp_root_oclass,
.head.vblank_init = nv50_disp_vblank_init,
.head.vblank_fini = nv50_disp_vblank_fini,
.head.scanoutpos = nv50_disp_root_scanoutpos,
.outp.internal.crt = nv50_dac_output_new,
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.power = nv50_dac_power,
.dac.sense = nv50_dac_sense,
.sor.nr = 4,
.sor.power = nv50_sor_power,
.sor.hda_eld = gt215_hda_eld,
.sor.hdmi = gt215_hdmi_ctrl,
.pior.nr = 3,
.pior.power = nv50_pior_power,
}; };
static int int
gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt215_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nv50_disp *disp; return nv50_disp_new_(&gt215_disp, device, index, 2, pdisp);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->base.func = &gt215_disp_func;
ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
if (ret)
return ret;
nv_subdev(disp)->intr = nv50_disp_intr;
INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
disp->head.nr = 2;
disp->dac.nr = 3;
disp->sor.nr = 4;
disp->pior.nr = 3;
disp->dac.power = nv50_dac_power;
disp->dac.sense = nv50_dac_sense;
disp->sor.power = nv50_sor_power;
disp->sor.hda_eld = gt215_hda_eld;
disp->sor.hdmi = gt215_hdmi_ctrl;
disp->pior.power = nv50_pior_power;
return 0;
} }
struct nvkm_oclass *
gt215_disp_oclass = &(struct nv50_disp_impl) {
.base.base.handle = NV_ENGINE(DISP, 0x85),
.base.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gt215_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.base.outp.internal.crt = nv50_dac_output_new,
.base.outp.internal.tmds = nv50_sor_output_new,
.base.outp.internal.lvds = nv50_sor_output_new,
.base.outp.internal.dp = g94_sor_dp_new,
.base.outp.external.lvds = nv50_pior_output_new,
.base.outp.external.dp = nv50_pior_dp_new,
.base.vblank = &nv50_disp_vblank_func,
.head.scanoutpos = nv50_disp_root_scanoutpos,
}.base.base;
...@@ -23,34 +23,31 @@ ...@@ -23,34 +23,31 @@
*/ */
#include "priv.h" #include "priv.h"
static const struct nvkm_disp_oclass *
nv04_disp_root(struct nvkm_disp *disp)
{
return &nv04_disp_root_oclass;
}
static void static void
nv04_disp_vblank_init(struct nvkm_event *event, int type, int head) nv04_disp_vblank_init(struct nvkm_disp *disp, int head)
{ {
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
struct nvkm_device *device = disp->engine.subdev.device; struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001); nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001);
} }
static void static void
nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head) nv04_disp_vblank_fini(struct nvkm_disp *disp, int head)
{ {
struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
struct nvkm_device *device = disp->engine.subdev.device; struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000); nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000);
} }
static const struct nvkm_event_func
nv04_disp_vblank_func = {
.ctor = nvkm_disp_vblank_ctor,
.init = nv04_disp_vblank_init,
.fini = nv04_disp_vblank_fini,
};
static void static void
nv04_disp_intr(struct nvkm_subdev *subdev) nv04_disp_intr(struct nvkm_disp *disp)
{ {
struct nvkm_disp *disp = (void *)subdev; struct nvkm_subdev *subdev = &disp->engine.subdev;
struct nvkm_device *device = disp->engine.subdev.device; struct nvkm_device *device = subdev->device;
u32 crtc0 = nvkm_rd32(device, 0x600100); u32 crtc0 = nvkm_rd32(device, 0x600100);
u32 crtc1 = nvkm_rd32(device, 0x602100); u32 crtc1 = nvkm_rd32(device, 0x602100);
u32 pvideo; u32 pvideo;
...@@ -65,8 +62,7 @@ nv04_disp_intr(struct nvkm_subdev *subdev) ...@@ -65,8 +62,7 @@ nv04_disp_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, 0x602100, 0x00000001); nvkm_wr32(device, 0x602100, 0x00000001);
} }
if (nv_device(disp)->chipset >= 0x10 && if (device->chipset >= 0x10 && device->chipset <= 0x40) {
nv_device(disp)->chipset <= 0x40) {
pvideo = nvkm_rd32(device, 0x8100); pvideo = nvkm_rd32(device, 0x8100);
if (pvideo & ~0x11) if (pvideo & ~0x11)
nvkm_info(subdev, "PVIDEO intr: %08x\n", pvideo); nvkm_info(subdev, "PVIDEO intr: %08x\n", pvideo);
...@@ -76,37 +72,14 @@ nv04_disp_intr(struct nvkm_subdev *subdev) ...@@ -76,37 +72,14 @@ nv04_disp_intr(struct nvkm_subdev *subdev)
static const struct nvkm_disp_func static const struct nvkm_disp_func
nv04_disp = { nv04_disp = {
.root = &nv04_disp_root_oclass, .intr = nv04_disp_intr,
.root = nv04_disp_root,
.head.vblank_init = nv04_disp_vblank_init,
.head.vblank_fini = nv04_disp_vblank_fini,
}; };
static int int
nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{ {
struct nvkm_disp *disp; return nvkm_disp_new_(&nv04_disp, device, index, 2, pdisp);
int ret;
ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
"display", &disp);
*pobject = nv_object(disp);
if (ret)
return ret;
disp->func = &nv04_disp;
nv_subdev(disp)->intr = nv04_disp_intr;
return 0;
} }
struct nvkm_oclass *
nv04_disp_oclass = &(struct nvkm_disp_impl) {
.base.handle = NV_ENGINE(DISP, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_disp_ctor,
.dtor = _nvkm_disp_dtor,
.init = _nvkm_disp_init,
.fini = _nvkm_disp_fini,
},
.vblank = &nv04_disp_vblank_func,
}.base;
...@@ -11,6 +11,7 @@ struct nvkm_output_dp; ...@@ -11,6 +11,7 @@ struct nvkm_output_dp;
#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp #define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
struct nv50_disp { struct nv50_disp {
const struct nv50_disp_func *func;
struct nvkm_disp base; struct nvkm_disp base;
struct work_struct supervisor; struct work_struct supervisor;
...@@ -19,37 +20,16 @@ struct nv50_disp { ...@@ -19,37 +20,16 @@ struct nv50_disp {
struct nvkm_event uevent; struct nvkm_event uevent;
struct { struct {
int nr;
} head;
struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
int (*sense)(NV50_DISP_MTHD_V1);
} dac;
struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
int (*hda_eld)(NV50_DISP_MTHD_V1);
int (*hdmi)(NV50_DISP_MTHD_V1);
u32 lvdsconf; u32 lvdsconf;
void (*magic)(struct nvkm_output *);
} sor; } sor;
struct { struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
u8 type[3]; u8 type[3];
} pior; } pior;
struct nv50_disp_chan *chan[17]; struct nv50_disp_chan *chan[17];
}; };
struct nv50_disp_impl {
struct nvkm_disp_impl base;
struct {
int (*scanoutpos)(NV50_DISP_MTHD_V0);
} head;
};
int nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0); int nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
int gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0); int gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
...@@ -68,11 +48,70 @@ int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1); ...@@ -68,11 +48,70 @@ int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1);
int nv50_sor_power(NV50_DISP_MTHD_V1); int nv50_sor_power(NV50_DISP_MTHD_V1);
int nv50_pior_power(NV50_DISP_MTHD_V1); int nv50_pior_power(NV50_DISP_MTHD_V1);
int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
int index, int heads, struct nvkm_disp **);
int gf119_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
int index, struct nvkm_disp **);
struct nv50_disp_func_outp {
int (* crt)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
int (* tv)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
int (*tmds)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
int (*lvds)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
int (* dp)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
};
struct nv50_disp_func {
void (*intr)(struct nv50_disp *);
const struct nvkm_event_func *uevent;
void (*super)(struct work_struct *);
const struct nvkm_disp_oclass *root;
struct {
void (*vblank_init)(struct nv50_disp *, int head);
void (*vblank_fini)(struct nv50_disp *, int head);
int (*scanoutpos)(NV50_DISP_MTHD_V0);
} head;
struct {
const struct nv50_disp_func_outp internal;
const struct nv50_disp_func_outp external;
} outp;
struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
int (*sense)(NV50_DISP_MTHD_V1);
} dac;
struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
int (*hda_eld)(NV50_DISP_MTHD_V1);
int (*hdmi)(NV50_DISP_MTHD_V1);
void (*magic)(struct nvkm_output *);
} sor;
struct {
int nr;
int (*power)(NV50_DISP_MTHD_V1);
} pior;
};
void nv50_disp_vblank_init(struct nv50_disp *, int);
void nv50_disp_vblank_fini(struct nv50_disp *, int);
void nv50_disp_intr(struct nv50_disp *);
void nv50_disp_intr_supervisor(struct work_struct *); void nv50_disp_intr_supervisor(struct work_struct *);
void nv50_disp_intr(struct nvkm_subdev *);
extern const struct nvkm_event_func nv50_disp_vblank_func;
void gf119_disp_vblank_init(struct nv50_disp *, int);
void gf119_disp_vblank_fini(struct nv50_disp *, int);
void gf119_disp_intr(struct nv50_disp *);
void gf119_disp_intr_supervisor(struct work_struct *); void gf119_disp_intr_supervisor(struct work_struct *);
void gf119_disp_intr(struct nvkm_subdev *);
extern const struct nvkm_event_func gf119_disp_vblank_func;
#endif #endif
...@@ -47,7 +47,7 @@ nv50_disp_oimm_new(const struct nv50_disp_chan_func *func, ...@@ -47,7 +47,7 @@ nv50_disp_oimm_new(const struct nv50_disp_chan_func *func,
if (nvif_unpack(args->v0, 0, 0, false)) { if (nvif_unpack(args->v0, 0, 0, false)) {
nvif_ioctl(parent, "create disp overlay vers %d head %d\n", nvif_ioctl(parent, "create disp overlay vers %d head %d\n",
args->v0.version, args->v0.head); args->v0.version, args->v0.head);
if (args->v0.head > disp->head.nr) if (args->v0.head > disp->base.head.nr)
return -EINVAL; return -EINVAL;
head = args->v0.head; head = args->v0.head;
} else } else
......
...@@ -49,7 +49,7 @@ nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func, ...@@ -49,7 +49,7 @@ nv50_disp_ovly_new(const struct nv50_disp_dmac_func *func,
nvif_ioctl(parent, "create disp overlay channel dma vers %d " nvif_ioctl(parent, "create disp overlay channel dma vers %d "
"pushbuf %016llx head %d\n", "pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head); args->v0.version, args->v0.pushbuf, args->v0.head);
if (args->v0.head > disp->head.nr) if (args->v0.head > disp->base.head.nr)
return -EINVAL; return -EINVAL;
push = args->v0.pushbuf; push = args->v0.pushbuf;
head = args->v0.head; head = args->v0.head;
......
...@@ -4,6 +4,12 @@ ...@@ -4,6 +4,12 @@
#include "outp.h" #include "outp.h"
#include "outpdp.h" #include "outpdp.h"
int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *,
int index, int heads, struct nvkm_disp *);
int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *,
int index, int heads, struct nvkm_disp **);
void nvkm_disp_vblank(struct nvkm_disp *, int head);
struct nvkm_disp_func_outp { struct nvkm_disp_func_outp {
int (* crt)(struct nvkm_disp *, int index, struct dcb_output *, int (* crt)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **); struct nvkm_output **);
...@@ -17,44 +23,23 @@ struct nvkm_disp_func_outp { ...@@ -17,44 +23,23 @@ struct nvkm_disp_func_outp {
struct nvkm_output **); struct nvkm_output **);
}; };
struct nvkm_disp_impl { struct nvkm_disp_func {
struct nvkm_oclass base; void *(*dtor)(struct nvkm_disp *);
void (*intr)(struct nvkm_disp *);
const struct nvkm_disp_oclass *(*root)(struct nvkm_disp *);
struct {
void (*vblank_init)(struct nvkm_disp *, int head);
void (*vblank_fini)(struct nvkm_disp *, int head);
} head;
struct { struct {
const struct nvkm_disp_func_outp internal; const struct nvkm_disp_func_outp internal;
const struct nvkm_disp_func_outp external; const struct nvkm_disp_func_outp external;
} outp; } outp;
const struct nvkm_event_func *vblank;
}; };
#define nvkm_disp_create(p,e,c,h,i,x,d) \
nvkm_disp_create_((p), (e), (c), (h), (i), (x), \
sizeof(**d), (void **)d)
#define nvkm_disp_destroy(d) ({ \
struct nvkm_disp *disp = (d); \
_nvkm_disp_dtor(nv_object(disp)); \
})
#define nvkm_disp_init(d) ({ \
struct nvkm_disp *disp = (d); \
_nvkm_disp_init(nv_object(disp)); \
})
#define nvkm_disp_fini(d,s) ({ \
struct nvkm_disp *disp = (d); \
_nvkm_disp_fini(nv_object(disp), (s)); \
})
int nvkm_disp_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int heads,
const char *, const char *, int, void **);
void _nvkm_disp_dtor(struct nvkm_object *);
int _nvkm_disp_init(struct nvkm_object *);
int _nvkm_disp_fini(struct nvkm_object *, bool);
extern struct nvkm_oclass *nvkm_output_oclass;
extern struct nvkm_oclass *nvkm_connector_oclass;
int nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size,
struct nvkm_notify *);
void nvkm_disp_vblank(struct nvkm_disp *, int head);
int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **); int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
extern const struct nvkm_disp_oclass nv04_disp_root_oclass; extern const struct nvkm_disp_oclass nv04_disp_root_oclass;
......
...@@ -87,7 +87,7 @@ gf119_disp_root_init(struct nv50_disp_root *root) ...@@ -87,7 +87,7 @@ gf119_disp_root_init(struct nv50_disp_root *root)
*/ */
/* ... CRTC caps */ /* ... CRTC caps */
for (i = 0; i < disp->head.nr; i++) { for (i = 0; i < disp->base.head.nr; i++) {
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800)); tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp); nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
tmp = nvkm_rd32(device, 0x616108 + (i * 0x800)); tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
...@@ -97,13 +97,13 @@ gf119_disp_root_init(struct nv50_disp_root *root) ...@@ -97,13 +97,13 @@ gf119_disp_root_init(struct nv50_disp_root *root)
} }
/* ... DAC caps */ /* ... DAC caps */
for (i = 0; i < disp->dac.nr; i++) { for (i = 0; i < disp->func->dac.nr; i++) {
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp); nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
} }
/* ... SOR caps */ /* ... SOR caps */
for (i = 0; i < disp->sor.nr; i++) { for (i = 0; i < disp->func->sor.nr; i++) {
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp); nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
} }
...@@ -133,7 +133,7 @@ gf119_disp_root_init(struct nv50_disp_root *root) ...@@ -133,7 +133,7 @@ gf119_disp_root_init(struct nv50_disp_root *root)
* *
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
*/ */
for (i = 0; i < disp->head.nr; i++) for (i = 0; i < disp->base.head.nr; i++)
nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
return 0; return 0;
......
...@@ -74,7 +74,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) ...@@ -74,7 +74,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
} *args = data; } *args = data;
struct nv50_disp_root *root = nv50_disp_root(object); struct nv50_disp_root *root = nv50_disp_root(object);
struct nv50_disp *disp = root->disp; struct nv50_disp *disp = root->disp;
const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); const struct nv50_disp_func *func = disp->func;
struct nvkm_output *outp = NULL; struct nvkm_output *outp = NULL;
struct nvkm_output *temp; struct nvkm_output *temp;
u16 type, mask = 0; u16 type, mask = 0;
...@@ -102,7 +102,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) ...@@ -102,7 +102,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
} else } else
return ret; return ret;
if (head < 0 || head >= disp->head.nr) if (head < 0 || head >= disp->base.head.nr)
return -ENXIO; return -ENXIO;
if (mask) { if (mask) {
...@@ -119,26 +119,26 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) ...@@ -119,26 +119,26 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
switch (mthd) { switch (mthd) {
case NV50_DISP_SCANOUTPOS: case NV50_DISP_SCANOUTPOS:
return impl->head.scanoutpos(object, disp, data, size, head); return func->head.scanoutpos(object, disp, data, size, head);
default: default:
break; break;
} }
switch (mthd * !!outp) { switch (mthd * !!outp) {
case NV50_DISP_MTHD_V1_DAC_PWR: case NV50_DISP_MTHD_V1_DAC_PWR:
return disp->dac.power(object, disp, data, size, head, outp); return func->dac.power(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_DAC_LOAD: case NV50_DISP_MTHD_V1_DAC_LOAD:
return disp->dac.sense(object, disp, data, size, head, outp); return func->dac.sense(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_PWR: case NV50_DISP_MTHD_V1_SOR_PWR:
return disp->sor.power(object, disp, data, size, head, outp); return func->sor.power(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_HDA_ELD: case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
if (!disp->sor.hda_eld) if (!func->sor.hda_eld)
return -ENODEV; return -ENODEV;
return disp->sor.hda_eld(object, disp, data, size, head, outp); return func->sor.hda_eld(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_HDMI_PWR: case NV50_DISP_MTHD_V1_SOR_HDMI_PWR:
if (!disp->sor.hdmi) if (!func->sor.hdmi)
return -ENODEV; return -ENODEV;
return disp->sor.hdmi(object, disp, data, size, head, outp); return func->sor.hdmi(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: { case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
union { union {
struct nv50_disp_sor_lvds_script_v0 v0; struct nv50_disp_sor_lvds_script_v0 v0;
...@@ -178,9 +178,9 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) ...@@ -178,9 +178,9 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
} }
break; break;
case NV50_DISP_MTHD_V1_PIOR_PWR: case NV50_DISP_MTHD_V1_PIOR_PWR:
if (!disp->pior.power) if (!func->pior.power)
return -ENODEV; return -ENODEV;
return disp->pior.power(object, disp, data, size, head, outp); return func->pior.power(object, disp, data, size, head, outp);
default: default:
break; break;
} }
...@@ -318,7 +318,7 @@ nv50_disp_root_init(struct nv50_disp_root *root) ...@@ -318,7 +318,7 @@ nv50_disp_root_init(struct nv50_disp_root *root)
nvkm_wr32(device, 0x610184, tmp); nvkm_wr32(device, 0x610184, tmp);
/* ... CRTC caps */ /* ... CRTC caps */
for (i = 0; i < disp->head.nr; i++) { for (i = 0; i < disp->base.head.nr; i++) {
tmp = nvkm_rd32(device, 0x616100 + (i * 0x800)); tmp = nvkm_rd32(device, 0x616100 + (i * 0x800));
nvkm_wr32(device, 0x610190 + (i * 0x10), tmp); nvkm_wr32(device, 0x610190 + (i * 0x10), tmp);
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800)); tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
...@@ -330,19 +330,19 @@ nv50_disp_root_init(struct nv50_disp_root *root) ...@@ -330,19 +330,19 @@ nv50_disp_root_init(struct nv50_disp_root *root)
} }
/* ... DAC caps */ /* ... DAC caps */
for (i = 0; i < disp->dac.nr; i++) { for (i = 0; i < disp->func->dac.nr; i++) {
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp); nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp);
} }
/* ... SOR caps */ /* ... SOR caps */
for (i = 0; i < disp->sor.nr; i++) { for (i = 0; i < disp->func->sor.nr; i++) {
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp); nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp);
} }
/* ... PIOR caps */ /* ... PIOR caps */
for (i = 0; i < disp->pior.nr; i++) { for (i = 0; i < disp->func->pior.nr; i++) {
tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800)); tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800));
nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp); nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp);
} }
......
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