Commit 736a4aad authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'renesas-fixes-for-v6.6-tag3' of...

Merge tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes

Renesas fixes for v6.6 (take three)

  - Sort out a few Kconfig dependency issues for the rich set of RISC-V
    non-coherent DMA support.

* tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
  riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
  riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT

Link: https://lore.kernel.org/r/cover.1698312384.git.geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 291c0d3a 9eab43fa
...@@ -273,11 +273,9 @@ config RISCV_DMA_NONCOHERENT ...@@ -273,11 +273,9 @@ config RISCV_DMA_NONCOHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
select DMA_DIRECT_REMAP if MMU
config RISCV_NONSTANDARD_CACHE_OPS config RISCV_NONSTANDARD_CACHE_OPS
bool bool
depends on RISCV_DMA_NONCOHERENT
help help
This enables function pointer support for non-standard noncoherent This enables function pointer support for non-standard noncoherent
systems to handle cache management. systems to handle cache management.
...@@ -550,6 +548,7 @@ config RISCV_ISA_ZICBOM ...@@ -550,6 +548,7 @@ config RISCV_ISA_ZICBOM
depends on RISCV_ALTERNATIVE depends on RISCV_ALTERNATIVE
default y default y
select RISCV_DMA_NONCOHERENT select RISCV_DMA_NONCOHERENT
select DMA_DIRECT_REMAP
help help
Adds support to dynamically detect the presence of the ZICBOM Adds support to dynamically detect the presence of the ZICBOM
extension (Cache Block Management Operations) and enable its extension (Cache Block Management Operations) and enable its
......
...@@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT ...@@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT
config ERRATA_THEAD_CMO config ERRATA_THEAD_CMO
bool "Apply T-Head cache management errata" bool "Apply T-Head cache management errata"
depends on ERRATA_THEAD && MMU depends on ERRATA_THEAD && MMU
select DMA_DIRECT_REMAP
select RISCV_DMA_NONCOHERENT select RISCV_DMA_NONCOHERENT
default y default y
help help
......
...@@ -3,7 +3,7 @@ menu "Cache Drivers" ...@@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller" bool "Andes Technology AX45MP L2 Cache controller"
depends on RISCV_DMA_NONCOHERENT depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS select RISCV_NONSTANDARD_CACHE_OPS
help help
Support for the L2 cache controller on Andes Technology AX45MP platforms. Support for the L2 cache controller on Andes Technology AX45MP platforms.
......
...@@ -335,6 +335,7 @@ config ARCH_R9A07G043 ...@@ -335,6 +335,7 @@ config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five" bool "RISC-V Platform support for RZ/Five"
depends on NONPORTABLE depends on NONPORTABLE
depends on RISCV_ALTERNATIVE depends on RISCV_ALTERNATIVE
depends on !RISCV_ISA_ZICBOM
depends on RISCV_SBI depends on RISCV_SBI
select ARCH_RZG2L select ARCH_RZG2L
select AX45MP_L2_CACHE select AX45MP_L2_CACHE
......
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