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Commit 74b14e28 authored by Vlad.Karpovich's avatar Vlad.Karpovich Committed by Mark Brown
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ASoC: cs35l45: DSP Support 

The CS35L45 digital core incorporates one programmable DSP block,
capable of running a wide range of audio enhancement and speaker
and battery protection functions.
Signed-off-by: default avatarVlad Karpovich <vkarpovi@opensource.cirrus.com>
Link: https://lore.kernel.org/r/167933510679.26.5992985447093367768@mailman-core.alsa-project.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6085f9e6
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Showing with 579 additions and 13 deletions
sound/soc/codecs/Kconfig
View file @ 74b14e28
......@@ -364,6 +364,8 @@ config SND_SOC_WM_ADSP
default y if SND_SOC_WM2200=y
default y if SND_SOC_CS35L41_SPI=y
default y if SND_SOC_CS35L41_I2C=y
default y if SND_SOC_CS35L45_SPI=y
default y if SND_SOC_CS35L45_I2C=y
default m if SND_SOC_MADERA=m
default m if SND_SOC_CS47L24=m
default m if SND_SOC_WM5102=m
......@@ -371,6 +373,8 @@ config SND_SOC_WM_ADSP
default m if SND_SOC_WM2200=m
default m if SND_SOC_CS35L41_SPI=m
default m if SND_SOC_CS35L41_I2C=m
default m if SND_SOC_CS35L45_SPI=m
default m if SND_SOC_CS35L45_I2C=m
config SND_SOC_AB8500_CODEC
tristate
......
sound/soc/codecs/cs35l45-spi.c
View file @ 74b14e28
......@@ -23,6 +23,9 @@ static int cs35l45_spi_probe(struct spi_device *spi)
if (cs35l45 == NULL)
return -ENOMEM;
spi->max_speed_hz = CS35L45_SPI_MAX_FREQ;
spi_setup(spi);
spi_set_drvdata(spi, cs35l45);
cs35l45->regmap = devm_regmap_init_spi(spi, &cs35l45_spi_regmap);
if (IS_ERR(cs35l45->regmap)) {
......
sound/soc/codecs/cs35l45-tables.c
View file @ 74b14e28
......@@ -46,6 +46,7 @@ static const struct reg_default cs35l45_defaults[] = {
{ CS35L45_SYNC_GPIO1, 0x00000007 },
{ CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
{ CS35L45_GPIO3, 0x00000005 },
{ CS35L45_PWRMGT_CTL, 0x00000000 },
{ CS35L45_REFCLK_INPUT, 0x00000510 },
{ CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
{ CS35L45_ASP_ENABLES1, 0x00000000 },
......@@ -63,6 +64,30 @@ static const struct reg_default cs35l45_defaults[] = {
{ CS35L45_ASPTX3_INPUT, 0x00000020 },
{ CS35L45_ASPTX4_INPUT, 0x00000028 },
{ CS35L45_ASPTX5_INPUT, 0x00000048 },
{ CS35L45_DSP1_RX1_RATE, 0x00000001 },
{ CS35L45_DSP1_RX2_RATE, 0x00000001 },
{ CS35L45_DSP1_RX3_RATE, 0x00000001 },
{ CS35L45_DSP1_RX4_RATE, 0x00000001 },
{ CS35L45_DSP1_RX5_RATE, 0x00000001 },
{ CS35L45_DSP1_RX6_RATE, 0x00000001 },
{ CS35L45_DSP1_RX7_RATE, 0x00000001 },
{ CS35L45_DSP1_RX8_RATE, 0x00000001 },
{ CS35L45_DSP1_TX1_RATE, 0x00000001 },
{ CS35L45_DSP1_TX2_RATE, 0x00000001 },
{ CS35L45_DSP1_TX3_RATE, 0x00000001 },
{ CS35L45_DSP1_TX4_RATE, 0x00000001 },
{ CS35L45_DSP1_TX5_RATE, 0x00000001 },
{ CS35L45_DSP1_TX6_RATE, 0x00000001 },
{ CS35L45_DSP1_TX7_RATE, 0x00000001 },
{ CS35L45_DSP1_TX8_RATE, 0x00000001 },
{ CS35L45_DSP1RX1_INPUT, 0x00000008 },
{ CS35L45_DSP1RX2_INPUT, 0x00000009 },
{ CS35L45_DSP1RX3_INPUT, 0x00000018 },
{ CS35L45_DSP1RX4_INPUT, 0x00000019 },
{ CS35L45_DSP1RX5_INPUT, 0x00000020 },
{ CS35L45_DSP1RX6_INPUT, 0x00000028 },
{ CS35L45_DSP1RX7_INPUT, 0x0000003A },
{ CS35L45_DSP1RX8_INPUT, 0x00000028 },
{ CS35L45_AMP_PCM_CONTROL, 0x00100000 },
{ CS35L45_IRQ1_CFG, 0x00000000 },
{ CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
......@@ -100,6 +125,7 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
case CS35L45_SYNC_GPIO1:
case CS35L45_INTB_GPIO2_MCLK_REF:
case CS35L45_GPIO3:
case CS35L45_PWRMGT_CTL:
case CS35L45_REFCLK_INPUT:
case CS35L45_GLOBAL_SAMPLE_RATE:
case CS35L45_ASP_ENABLES1:
......@@ -117,6 +143,14 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
case CS35L45_ASPTX3_INPUT:
case CS35L45_ASPTX4_INPUT:
case CS35L45_ASPTX5_INPUT:
case CS35L45_DSP1RX1_INPUT:
case CS35L45_DSP1RX2_INPUT:
case CS35L45_DSP1RX3_INPUT:
case CS35L45_DSP1RX4_INPUT:
case CS35L45_DSP1RX5_INPUT:
case CS35L45_DSP1RX6_INPUT:
case CS35L45_DSP1RX7_INPUT:
case CS35L45_DSP1RX8_INPUT:
case CS35L45_AMP_PCM_CONTROL:
case CS35L45_AMP_PCM_HPF_TST:
case CS35L45_IRQ1_CFG:
......@@ -128,6 +162,40 @@ static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
case CS35L45_GPIO1_CTRL1:
case CS35L45_GPIO2_CTRL1:
case CS35L45_GPIO3_CTRL1:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP1_SYS_ID:
case CS35L45_DSP1_CLOCK_FREQ:
case CS35L45_DSP1_RX1_RATE:
case CS35L45_DSP1_RX2_RATE:
case CS35L45_DSP1_RX3_RATE:
case CS35L45_DSP1_RX4_RATE:
case CS35L45_DSP1_RX5_RATE:
case CS35L45_DSP1_RX6_RATE:
case CS35L45_DSP1_RX7_RATE:
case CS35L45_DSP1_RX8_RATE:
case CS35L45_DSP1_TX1_RATE:
case CS35L45_DSP1_TX2_RATE:
case CS35L45_DSP1_TX3_RATE:
case CS35L45_DSP1_TX4_RATE:
case CS35L45_DSP1_TX5_RATE:
case CS35L45_DSP1_TX6_RATE:
case CS35L45_DSP1_TX7_RATE:
case CS35L45_DSP1_TX8_RATE:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_CCM_CORE_CONTROL:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
......@@ -146,6 +214,24 @@ static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
case CS35L45_GPIO_STATUS1:
case CS35L45_DSP_MBOX_1:
case CS35L45_DSP_MBOX_2:
case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:
case CS35L45_DSP1_SYS_ID:
case CS35L45_DSP1_CLOCK_FREQ:
case CS35L45_DSP1_SCRATCH1:
case CS35L45_DSP1_SCRATCH2:
case CS35L45_DSP1_SCRATCH3:
case CS35L45_DSP1_SCRATCH4:
case CS35L45_DSP1_CCM_CORE_CONTROL:
case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607:
case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071:
case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143:
case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532:
case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022:
case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043:
case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834:
return true;
default:
return false;
......
sound/soc/codecs/cs35l45.c
View file @ 74b14e28
This diff is collapsed.
sound/soc/codecs/cs35l45.h
View file @ 74b14e28
......@@ -15,6 +15,7 @@
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <dt-bindings/sound/cs35l45.h>
#include "wm_adsp.h"
#define CS35L45_DEVID 0x00000000
#define CS35L45_REVID 0x00000004
......@@ -28,6 +29,7 @@
#define CS35L45_SYNC_GPIO1 0x00002430
#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434
#define CS35L45_GPIO3 0x00002438
#define CS35L45_PWRMGT_CTL 0x00002900
#define CS35L45_REFCLK_INPUT 0x00002C04
#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C
#define CS35L45_BOOST_CCM_CFG 0x00003808
......@@ -48,6 +50,14 @@
#define CS35L45_ASPTX3_INPUT 0x00004C28
#define CS35L45_ASPTX4_INPUT 0x00004C2C
#define CS35L45_ASPTX5_INPUT 0x00004C30
#define CS35L45_DSP1RX1_INPUT 0x00004C40
#define CS35L45_DSP1RX2_INPUT 0x00004C44
#define CS35L45_DSP1RX3_INPUT 0x00004C48
#define CS35L45_DSP1RX4_INPUT 0x00004C4C
#define CS35L45_DSP1RX5_INPUT 0x00004C50
#define CS35L45_DSP1RX6_INPUT 0x00004C54
#define CS35L45_DSP1RX7_INPUT 0x00004C58
#define CS35L45_DSP1RX8_INPUT 0x00004C5C
#define CS35L45_LDPM_CONFIG 0x00006404
#define CS35L45_AMP_PCM_CONTROL 0x00007000
#define CS35L45_AMP_PCM_HPF_TST 0x00007004
......@@ -91,7 +101,55 @@
#define CS35L45_GPIO1_CTRL1 0x0000F008
#define CS35L45_GPIO2_CTRL1 0x0000F00C
#define CS35L45_GPIO3_CTRL1 0x0000F010
#define CS35L45_LASTREG 0x0000F010
#define CS35L45_DSP_MBOX_1 0x00011000
#define CS35L45_DSP_MBOX_2 0x00011004
#define CS35L45_DSP_VIRT1_MBOX_1 0x00011020
#define CS35L45_DSP_VIRT1_MBOX_2 0x00011024
#define CS35L45_DSP_VIRT1_MBOX_3 0x00011028
#define CS35L45_DSP_VIRT1_MBOX_4 0x0001102C
#define CS35L45_DSP_VIRT2_MBOX_1 0x00011040
#define CS35L45_DSP_VIRT2_MBOX_2 0x00011044
#define CS35L45_DSP_VIRT2_MBOX_3 0x00011048
#define CS35L45_DSP_VIRT2_MBOX_4 0x0001104C
#define CS35L45_DSP1_XMEM_PACK_0 0x02000000
#define CS35L45_DSP1_XMEM_PACK_4607 0x020047FC
#define CS35L45_DSP1_XMEM_UNPACK32_0 0x02400000
#define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC
#define CS35L45_DSP1_SYS_ID 0x025E0000
#define CS35L45_DSP1_XMEM_UNPACK24_0 0x02800000
#define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC
#define CS35L45_DSP1_CLOCK_FREQ 0x02B80000
#define CS35L45_DSP1_RX1_RATE 0x02B80080
#define CS35L45_DSP1_RX2_RATE 0x02B80088
#define CS35L45_DSP1_RX3_RATE 0x02B80090
#define CS35L45_DSP1_RX4_RATE 0x02B80098
#define CS35L45_DSP1_RX5_RATE 0x02B800A0
#define CS35L45_DSP1_RX6_RATE 0x02B800A8
#define CS35L45_DSP1_RX7_RATE 0x02B800B0
#define CS35L45_DSP1_RX8_RATE 0x02B800B8
#define CS35L45_DSP1_TX1_RATE 0x02B80280
#define CS35L45_DSP1_TX2_RATE 0x02B80288
#define CS35L45_DSP1_TX3_RATE 0x02B80290
#define CS35L45_DSP1_TX4_RATE 0x02B80298
#define CS35L45_DSP1_TX5_RATE 0x02B802A0
#define CS35L45_DSP1_TX6_RATE 0x02B802A8
#define CS35L45_DSP1_TX7_RATE 0x02B802B0
#define CS35L45_DSP1_TX8_RATE 0x02B802B8
#define CS35L45_DSP1_SCRATCH1 0x02B805C0
#define CS35L45_DSP1_SCRATCH2 0x02B805C8
#define CS35L45_DSP1_SCRATCH3 0x02B805D0
#define CS35L45_DSP1_SCRATCH4 0x02B805D8
#define CS35L45_DSP1_CCM_CORE_CONTROL 0x02BC1000
#define CS35L45_DSP1_YMEM_PACK_0 0x02C00000
#define CS35L45_DSP1_YMEM_PACK_1532 0x02C017F0
#define CS35L45_DSP1_YMEM_UNPACK32_0 0x03000000
#define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8
#define CS35L45_DSP1_YMEM_UNPACK24_0 0x03400000
#define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC
#define CS35L45_DSP1_PMEM_0 0x03800000
#define CS35L45_DSP1_PMEM_3834 0x03803BE8
#define CS35L45_LASTREG 0x03C6EFE8
/* SFT_RESET */
#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000
......@@ -112,9 +170,20 @@
/* BLOCK_ENABLES2 */
#define CS35L45_ASP_EN_SHIFT 27
#define CS35L45_MEM_RDY_SHIFT 1
#define CS35L45_MEM_RDY_MASK BIT(1)
/* ERROR_RELEASE */
#define CS35L45_GLOBAL_ERR_RLS_MASK BIT(11)
/* CCM_CORE */
#define CS35L45_CCM_CORE_RESET_SHIFT 9
#define CS35L45_CCM_CORE_RESET_MASK BIT(9)
#define CS35L45_CCM_PM_REMAP_SHIFT 7
#define CS35L45_CCM_PM_REMAP_MASK BIT(7)
#define CS35L45_CCM_CORE_EN_SHIFT 0
#define CS35L45_CCM_CORE_EN_MASK BIT(0)
/* REFCLK_INPUT */
#define CS35L45_PLL_FORCE_EN_SHIFT 16
#define CS35L45_PLL_FORCE_EN_MASK BIT(16)
......@@ -240,6 +309,8 @@
/* CS35L45_IRQ1_EINT_2 */
#define CS35L45_DSP_WDT_EXPIRE_SHIFT 4
#define CS35L45_DSP_WDT_EXPIRE_MASK BIT(4)
#define CS35L45_DSP_VIRT2_MBOX_SHIFT 21
#define CS35L45_DSP_VIRT2_MBOX_MASK BIT(21)
/* CS35L45_IRQ1_EINT_3 */
#define CS35L45_PLL_LOCK_FLAG_SHIFT 1
......@@ -266,6 +337,8 @@
#define CS35L45_PCM_SRC_CLASSH_TGT 0x21
#define CS35L45_PCM_SRC_VDD_BATTMON 0x28
#define CS35L45_PCM_SRC_VDD_BSTMON 0x29
#define CS35L45_PCM_SRC_DSP_TX1 0x32
#define CS35L45_PCM_SRC_DSP_TX2 0x33
#define CS35L45_PCM_SRC_TEMPMON 0x3A
#define CS35L45_PCM_SRC_INTERPOLATOR 0x40
#define CS35L45_PCM_SRC_IL_TARGET 0x48
......@@ -275,6 +348,27 @@
#define CS35L45_POST_GLOBAL_EN_US 5000
#define CS35L45_PRE_GLOBAL_DIS_US 3000
#define CS35L45_SPI_MAX_FREQ 4000000
enum cs35l45_cspl_mboxstate {
CSPL_MBOX_STS_RUNNING = 0,
CSPL_MBOX_STS_PAUSED = 1,
CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
CSPL_MBOX_STS_HIBERNATE = 3,
};
enum cs35l45_cspl_mboxcmd {
CSPL_MBOX_CMD_NONE = 0,
CSPL_MBOX_CMD_PAUSE = 1,
CSPL_MBOX_CMD_RESUME = 2,
CSPL_MBOX_CMD_REINIT = 3,
CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
CSPL_MBOX_CMD_HIBERNATE = 5,
CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
};
#define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_3LE| \
SNDRV_PCM_FMTBIT_S24_LE)
......@@ -318,10 +412,22 @@ enum cs35l45_irq_list {
CS35L45_DSP_WDT_EXPIRE_IRQ,
CS35L45_PLL_UNLOCK_FLAG_RISE_IRQ,
CS35L45_PLL_LOCK_FLAG_IRQ,
CS35L45_DSP_VIRT2_MBOX_IRQ,
CS35L45_NUM_IRQ
};
#define CS35L45_MBOX3_CMD_MASK 0xFF
#define CS35L45_MBOX3_CMD_SHIFT 0
#define CS35L45_MBOX3_DATA_MASK 0xFFFFFF00
#define CS35L45_MBOX3_DATA_SHIFT 8
enum mbox3_events {
EVENT_SPEAKER_STATUS = 0x66,
EVENT_BOOT_DONE = 0x67,
};
struct cs35l45_private {
struct wm_adsp dsp; /* needs to be first member */
struct device *dev;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
......
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