Commit 763135b8 authored by Wolfram Sang's avatar Wolfram Sang Committed by Lee Jones

mfd: tmio: Sanitize comments

Reformat the comments to utilize the maximum line length and use single
line comments where appropriate. Remove superfluous comments, too.
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240213220221.2380-13-wsa+renesas@sang-engineering.comSigned-off-by: default avatarLee Jones <lee@kernel.org>
parent d411ccbe
...@@ -5,23 +5,23 @@ ...@@ -5,23 +5,23 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/types.h> #include <linux/types.h>
/* tmio MMC platform flags */ /* TMIO MMC platform flags */
/* /*
* Some controllers can support a 2-byte block size when the bus width * Some controllers can support a 2-byte block size when the bus width is
* is configured in 4-bit mode. * configured in 4-bit mode.
*/ */
#define TMIO_MMC_BLKSZ_2BYTES BIT(1) #define TMIO_MMC_BLKSZ_2BYTES BIT(1)
/*
* Some controllers can support SDIO IRQ signalling. /* Some controllers can support SDIO IRQ signalling */
*/
#define TMIO_MMC_SDIO_IRQ BIT(2) #define TMIO_MMC_SDIO_IRQ BIT(2)
/* Some features are only available or tested on R-Car Gen2 or later */ /* Some features are only available or tested on R-Car Gen2 or later */
#define TMIO_MMC_MIN_RCAR2 BIT(3) #define TMIO_MMC_MIN_RCAR2 BIT(3)
/* /*
* Some controllers require waiting for the SD bus to become * Some controllers require waiting for the SD bus to become idle before
* idle before writing to some registers. * writing to some registers.
*/ */
#define TMIO_MMC_HAS_IDLE_WAIT BIT(4) #define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
...@@ -32,31 +32,21 @@ ...@@ -32,31 +32,21 @@
*/ */
#define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5) #define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5)
/* /* Some controllers have CMD12 automatically issue/non-issue register */
* Some controllers have CMD12 automatically
* issue/non-issue register
*/
#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
/* Controller has some SDIO status bits which must be 1 */ /* Controller has some SDIO status bits which must be 1 */
#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
/* /* Some controllers have a 32-bit wide data port register */
* Some controllers have a 32-bit wide data port register
*/
#define TMIO_MMC_32BIT_DATA_PORT BIT(9) #define TMIO_MMC_32BIT_DATA_PORT BIT(9)
/* /* Some controllers allows to set SDx actual clock */
* Some controllers allows to set SDx actual clock
*/
#define TMIO_MMC_CLK_ACTUAL BIT(10) #define TMIO_MMC_CLK_ACTUAL BIT(10)
/* Some controllers have a CBSY bit */ /* Some controllers have a CBSY bit */
#define TMIO_MMC_HAVE_CBSY BIT(11) #define TMIO_MMC_HAVE_CBSY BIT(11)
/*
* data for the MMC controller
*/
struct tmio_mmc_data { struct tmio_mmc_data {
void *chan_priv_tx; void *chan_priv_tx;
void *chan_priv_rx; void *chan_priv_rx;
......
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