[Blackfin] arch: fix bug when DMA operation related core B of BF561
- Before DMA'ing data to core B L1 memory, caches have to be flushed. - Before DMA'ing data from core B L1 memory, caches have to be invalidated. - Fix lock/unlock. Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com> Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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