drm/amd/display: Create dcn401_clk_mgr struct

Create dcn401 specific structure to encapsulate version specific
variables.
Acked-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

@@ -367,14 +367,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 	break;
 
 	case AMDGPU_FAMILY_GC_12_0_0: {
-		struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
+		struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);
 
 		if (clk_mgr == NULL) {
 			BREAK_TO_DEBUGGER();
 			return NULL;
 		}
 
-		dcn401_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 		return &clk_mgr->base;
 	}
 	break;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

@@ -935,14 +935,18 @@ static struct clk_mgr_funcs dcn401_funcs = {
 		.is_smu_present = dcn401_is_smu_present,
 };
 
-void dcn401_clk_mgr_construct(
+struct clk_mgr_internal *dcn401_clk_mgr_construct(
 		struct dc_context *ctx,
-		struct clk_mgr_internal *clk_mgr,
-		struct pp_smu_funcs *pp_smu,
 		struct dccg *dccg)
 {
 	struct clk_log_info log_info = {0};
+	struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);
+	struct clk_mgr_internal *clk_mgr;
+
+	if (!clk_mgr401)
+		return NULL;
 
+	clk_mgr = &clk_mgr401->base;
 	clk_mgr->base.ctx = ctx;
 	clk_mgr->base.funcs = &dcn401_funcs;
 	clk_mgr->regs = &clk_mgr_regs_dcn401;
@@ -987,11 +991,24 @@ void dcn401_clk_mgr_construct(
 	clk_mgr->smu_present = false;
 
 	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
+	if (!clk_mgr->base.bw_params) {
+		BREAK_TO_DEBUGGER();
+		kfree(clk_mgr);
+		return NULL;
+	}
 
 	/* need physical address of table to give to PMFW */
 	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
 			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
 			&clk_mgr->wm_range_table_addr);
+	if (!clk_mgr->wm_range_table) {
+		BREAK_TO_DEBUGGER();
+		kfree(clk_mgr->base.bw_params);
+		return NULL;
+	}
+
+	return &clk_mgr401->base;
+
 }
 
 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

@@ -5,11 +5,13 @@
 #ifndef __DCN401_CLK_MGR_H_
 #define __DCN401_CLK_MGR_H_
 
+struct dcn401_clk_mgr {
+	struct clk_mgr_internal base;
+};
+
 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
 
-void dcn401_clk_mgr_construct(struct dc_context *ctx,
-		struct clk_mgr_internal *clk_mgr,
-		struct pp_smu_funcs *pp_smu,
+struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,
 		struct dccg *dccg);
 
 void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
@@ -17,6 +19,4 @@ void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 
 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
 
-
-
 #endif /* __DCN401_CLK_MGR_H_ */