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Commit 7c2b6c1e authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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media: atomisp: remove several duplicated files 

Those files have identical contents, but are located at
different parts of the driver. As their contents are identical,
we can simply remove them.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent c8b1a84e
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Showing with 9 additions and 6605 deletions
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c
View file @ 7c2b6c1e
......@@ -58,7 +58,7 @@
#include "ia_css_types.h"
#include "ia_css_stream.h"
#include "error_support.h"
#include "hrt/bits.h"
#include "bits.h"
/* We should never need to run the flash for more than 2 frames.
* At 15fps this means 133ms. We set the timeout a bit longer.
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifdef IA_CSS_INCLUDE_CONFIGURATIONS
#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h"
#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h"
#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h"
#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h"
#include "isp/kernels/output/output_1.0/ia_css_output.host.h"
#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h"
#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h"
/* ISP2401 */
#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h"
#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h"
#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h"
#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_CONFIG_H
#define _IA_CSS_ISP_CONFIG_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_configuration_ids {
IA_CSS_ITERATOR_CONFIG_ID,
IA_CSS_COPY_OUTPUT_CONFIG_ID,
IA_CSS_CROP_CONFIG_ID,
IA_CSS_FPN_CONFIG_ID,
IA_CSS_DVS_CONFIG_ID,
IA_CSS_QPLANE_CONFIG_ID,
IA_CSS_OUTPUT0_CONFIG_ID,
IA_CSS_OUTPUT1_CONFIG_ID,
IA_CSS_OUTPUT_CONFIG_ID,
IA_CSS_RAW_CONFIG_ID,
IA_CSS_TNR_CONFIG_ID,
IA_CSS_REF_CONFIG_ID,
IA_CSS_VF_CONFIG_ID,
/* ISP2401 */
IA_CSS_SC_CONFIG_ID,
IA_CSS_NUM_CONFIGURATION_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_config_memory_offsets {
struct {
struct ia_css_isp_parameter iterator;
struct ia_css_isp_parameter copy_output;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter dvs;
struct ia_css_isp_parameter qplane;
struct ia_css_isp_parameter output0;
struct ia_css_isp_parameter output1;
struct ia_css_isp_parameter output;
/* ISP2401 */
struct ia_css_isp_parameter sc;
struct ia_css_isp_parameter raw;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
struct ia_css_isp_parameter vf;
} dmem;
};
#if defined(IA_CSS_INCLUDE_CONFIGURATIONS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
/* ISP2401 */
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem);
#endif /* IA_CSS_INCLUDE_CONFIGURATION */
#endif /* _IA_CSS_ISP_CONFIG_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#define IA_CSS_INCLUDE_STATES
#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h"
#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h"
#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h"
#include "isp/kernels/de/de_1.0/ia_css_de.host.h"
#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h"
#include "isp/kernels/dpc2/ia_css_dpc2.host.h"
#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h"
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_STATE_H
#define _IA_CSS_ISP_STATE_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_state_ids {
IA_CSS_AA_STATE_ID,
IA_CSS_CNR_STATE_ID,
IA_CSS_CNR2_STATE_ID,
IA_CSS_DP_STATE_ID,
IA_CSS_DE_STATE_ID,
IA_CSS_TNR_STATE_ID,
IA_CSS_REF_STATE_ID,
IA_CSS_YNR_STATE_ID,
IA_CSS_NUM_STATE_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_state_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter cnr2;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ynr;
} vmem;
struct {
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
} dmem;
};
#if defined(IA_CSS_INCLUDE_STATES)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genstate.c:gen_state_init_table() */
extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(
const struct ia_css_binary *binary);
#endif /* IA_CSS_INCLUDE_STATE */
#endif /* _IA_CSS_ISP_STATE_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h
View file @ 7c2b6c1e
......@@ -28,7 +28,7 @@
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
/* This interface is deprecated */
#include "hrt/hive_types.h"
#include "hive_types.h"
/*
* Cell specific address maps
......
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_BITS_H
#define _HRT_BITS_H
#include "defs.h"
#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
#define _hrt_ones_0x0 0x00000000U
#define _hrt_ones_0x1 0x00000001U
#define _hrt_ones_0x2 0x00000003U
#define _hrt_ones_0x3 0x00000007U
#define _hrt_ones_0x4 0x0000000FU
#define _hrt_ones_0x5 0x0000001FU
#define _hrt_ones_0x6 0x0000003FU
#define _hrt_ones_0x7 0x0000007FU
#define _hrt_ones_0x8 0x000000FFU
#define _hrt_ones_0x9 0x000001FFU
#define _hrt_ones_0xA 0x000003FFU
#define _hrt_ones_0xB 0x000007FFU
#define _hrt_ones_0xC 0x00000FFFU
#define _hrt_ones_0xD 0x00001FFFU
#define _hrt_ones_0xE 0x00003FFFU
#define _hrt_ones_0xF 0x00007FFFU
#define _hrt_ones_0x10 0x0000FFFFU
#define _hrt_ones_0x11 0x0001FFFFU
#define _hrt_ones_0x12 0x0003FFFFU
#define _hrt_ones_0x13 0x0007FFFFU
#define _hrt_ones_0x14 0x000FFFFFU
#define _hrt_ones_0x15 0x001FFFFFU
#define _hrt_ones_0x16 0x003FFFFFU
#define _hrt_ones_0x17 0x007FFFFFU
#define _hrt_ones_0x18 0x00FFFFFFU
#define _hrt_ones_0x19 0x01FFFFFFU
#define _hrt_ones_0x1A 0x03FFFFFFU
#define _hrt_ones_0x1B 0x07FFFFFFU
#define _hrt_ones_0x1C 0x0FFFFFFFU
#define _hrt_ones_0x1D 0x1FFFFFFFU
#define _hrt_ones_0x1E 0x3FFFFFFFU
#define _hrt_ones_0x1F 0x7FFFFFFFU
#define _hrt_ones_0x20 0xFFFFFFFFU
#define _hrt_ones_0 _hrt_ones_0x0
#define _hrt_ones_1 _hrt_ones_0x1
#define _hrt_ones_2 _hrt_ones_0x2
#define _hrt_ones_3 _hrt_ones_0x3
#define _hrt_ones_4 _hrt_ones_0x4
#define _hrt_ones_5 _hrt_ones_0x5
#define _hrt_ones_6 _hrt_ones_0x6
#define _hrt_ones_7 _hrt_ones_0x7
#define _hrt_ones_8 _hrt_ones_0x8
#define _hrt_ones_9 _hrt_ones_0x9
#define _hrt_ones_10 _hrt_ones_0xA
#define _hrt_ones_11 _hrt_ones_0xB
#define _hrt_ones_12 _hrt_ones_0xC
#define _hrt_ones_13 _hrt_ones_0xD
#define _hrt_ones_14 _hrt_ones_0xE
#define _hrt_ones_15 _hrt_ones_0xF
#define _hrt_ones_16 _hrt_ones_0x10
#define _hrt_ones_17 _hrt_ones_0x11
#define _hrt_ones_18 _hrt_ones_0x12
#define _hrt_ones_19 _hrt_ones_0x13
#define _hrt_ones_20 _hrt_ones_0x14
#define _hrt_ones_21 _hrt_ones_0x15
#define _hrt_ones_22 _hrt_ones_0x16
#define _hrt_ones_23 _hrt_ones_0x17
#define _hrt_ones_24 _hrt_ones_0x18
#define _hrt_ones_25 _hrt_ones_0x19
#define _hrt_ones_26 _hrt_ones_0x1A
#define _hrt_ones_27 _hrt_ones_0x1B
#define _hrt_ones_28 _hrt_ones_0x1C
#define _hrt_ones_29 _hrt_ones_0x1D
#define _hrt_ones_30 _hrt_ones_0x1E
#define _hrt_ones_31 _hrt_ones_0x1F
#define _hrt_ones_32 _hrt_ones_0x20
#define _hrt_mask(b, n) \
(_hrt_ones(n) << (b))
#define _hrt_get_bits(w, b, n) \
(((w) >> (b)) & _hrt_ones(n))
#define _hrt_set_bits(w, b, n, v) \
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
_hrt_set_bits(w, 16, 16, v)
#endif /* _HRT_BITS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _cell_params_h
#define _cell_params_h
#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/
#define SP_ICACHE_TAG_BITS 4 /*size of tag*/
#define SP_ICACHE_SET_BITS 8 /* 256 sets*/
#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_2_DEPTH 0
#define SP_FIFO_3_DEPTH 0
#define SP_FIFO_4_DEPTH 0
#define SP_FIFO_5_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_DEFS_H_
#define _HRT_DEFS_H_
#ifndef HRTCAT
#define _HRTCAT(m, n) m##n
#define HRTCAT(m, n) _HRTCAT(m, n)
#endif
#ifndef HRTSTR
#define _HRTSTR(x) #x
#define HRTSTR(x) _HRTSTR(x)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#endif /* _HRT_DEFS_H_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _dma_v2_defs_h
#define _dma_v2_defs_h
#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels
#define _DMA_V2_CONNECTIONS_ID Connections
#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths
#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth
#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat
#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst
#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept
#define _DMA_V2_DEV_SRMD_ID DevSRMD
#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters
#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth
#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth
#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat
#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass
#define _DMA_V2_NO_PACK_ID has_no_pack
#define _DMA_V2_REG_ALIGN 4
#define _DMA_V2_REG_ADDR_BITS 2
/* Command word */
#define _DMA_V2_CMD_IDX 0
#define _DMA_V2_CMD_BITS 6
#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
#define _DMA_V2_CHANNEL_BITS 5
/* The command to set a parameter contains the PARAM field next */
#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_PARAM_BITS 4
/* Commands to read, write or init specific blocks contain these
three values */
#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_DEV_A_XB_BITS 8
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_CMD_CTRL_BITS 4
/* Packing setup word */
#define _DMA_V2_CONNECTION_IDX 0
#define _DMA_V2_CONNECTION_BITS 4
#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
#define _DMA_V2_EXTENSION_BITS 1
/* Elements packing word */
#define _DMA_V2_ELEMENTS_IDX 0
#define _DMA_V2_ELEMENTS_BITS 8
#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
#define _DMA_V2_LEFT_CROPPING_BITS 8
#define _DMA_V2_WIDTH_IDX 0
#define _DMA_V2_WIDTH_BITS 16
#define _DMA_V2_HEIGHT_IDX 0
#define _DMA_V2_HEIGHT_BITS 16
#define _DMA_V2_STRIDE_IDX 0
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_SIGN_EXTEND 1
/* SLAVE address map */
#define _DMA_V2_SEL_FSM_CMD 0
#define _DMA_V2_SEL_CH_REG 1
#define _DMA_V2_SEL_CONN_GROUP 2
#define _DMA_V2_SEL_DEV_INTERF 3
#define _DMA_V2_ADDR_SEL_COMP_IDX 12
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1
#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2
#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2
#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3
#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5
#endif /* _dma_v2_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_GDC_v2_defs_h_
#define HRT_GDC_v2_defs_h_
#define HRT_GDC_IS_V2
#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_REG_ID_POS 25
#define HRT_GDC_REG_ID_BITS 5
#define HRT_GDC_DATA_POS 0
#define HRT_GDC_DATA_BITS 25
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_PERF_1_1_pix 0
#define HRT_GDC_PERF_2_1_pix 1
#define HRT_GDC_PERF_1_2_pix 2
#define HRT_GDC_PERF_2_2_pix 3
#define HRT_GDC_NND_MODE 0
#define HRT_GDC_BLI_MODE 1
#define HRT_GDC_BCI_MODE 2
#define HRT_GDC_LUT_MODE 3
#define HRT_GDC_SCAN_STB 0
#define HRT_GDC_SCAN_STR 1
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
#define HRT_GDC_CE_OPY_LEN 14
#define HRT_GDC_CE_OPX_POS 16
#define HRT_GDC_CE_OPX_LEN 16
// CHK_ENGINE register bit-map:
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_BPP_IDX 3
#define HRT_GDC_FRYIPXFRX_IDX 4
#define HRT_GDC_OXDIM_IDX 5
#define HRT_GDC_OYDIM_IDX 6
#define HRT_GDC_SRC_ADDR_IDX 7
#define HRT_GDC_SRC_END_ADDR_IDX 8
#define HRT_GDC_SRC_WRAP_ADDR_IDX 9
#define HRT_GDC_SRC_STRIDE_IDX 10
#define HRT_GDC_DST_ADDR_IDX 11
#define HRT_GDC_DST_STRIDE_IDX 12
#define HRT_GDC_DX_IDX 13
#define HRT_GDC_DY_IDX 14
#define HRT_GDC_P0X_IDX 15
#define HRT_GDC_P0Y_IDX 16
#define HRT_GDC_P1X_IDX 17
#define HRT_GDC_P1Y_IDX 18
#define HRT_GDC_P2X_IDX 19
#define HRT_GDC_P2Y_IDX 20
#define HRT_GDC_P3X_IDX 21
#define HRT_GDC_P3Y_IDX 22
#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT
#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gp_timer_defs_h
#define _gp_timer_defs_h
#define _HRT_GP_TIMER_REG_ALIGN 4
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gpio_block_defs_h_
#define _gpio_block_defs_h_
#define _HRT_GPIO_BLOCK_REG_ALIGN 4
/* R/W registers */
#define _gpio_block_reg_do_e 0
#define _gpio_block_reg_do_select 1
#define _gpio_block_reg_do_0 2
#define _gpio_block_reg_do_1 3
#define _gpio_block_reg_do_pwm_cnt_0 4
#define _gpio_block_reg_do_pwm_cnt_1 5
#define _gpio_block_reg_do_pwm_cnt_2 6
#define _gpio_block_reg_do_pwm_cnt_3 7
#define _gpio_block_reg_do_pwm_main_cnt 8
#define _gpio_block_reg_do_pwm_enable 9
#define _gpio_block_reg_di_debounce_sel 10
#define _gpio_block_reg_di_debounce_cnt_0 11
#define _gpio_block_reg_di_debounce_cnt_1 12
#define _gpio_block_reg_di_debounce_cnt_2 13
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16
#endif /* _gpio_block_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
#define _HRTCAT3(m, n, o) m##n##o
#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
#define _HRTCAT4(m, n, o, p) m##n##o##p
#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
typedef unsigned int hive_bool;
#define hive_false 0
#define hive_true 1
typedef char hive_int8;
typedef short hive_int16;
typedef int hive_int32;
typedef long long hive_int64;
typedef unsigned char hive_uint8;
typedef unsigned short hive_uint16;
typedef unsigned int hive_uint32;
typedef unsigned long long hive_uint64;
/* by default assume 32 bit master port (both data and address) */
#ifndef HRT_DATA_WIDTH
#define HRT_DATA_WIDTH 32
#endif
#ifndef HRT_ADDRESS_WIDTH
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
#elif HRT_DATA_WIDTH == 32
typedef hive_uint32 hrt_data;
#else
#error data width not supported
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
#error adddres width not supported
#endif
/* The SP side representation of an HMM virtual address */
typedef hive_uint32 hrt_vaddress;
/* use 64 bit addresses in simulation, where possible */
typedef hive_uint64 hive_sim_address;
/* below is for csim, not for hrt, rename and move this elsewhere */
typedef unsigned int hive_uint;
typedef hive_uint32 hive_address;
typedef hive_address hive_slave_address;
typedef hive_address hive_mem_address;
/* MMIO devices */
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
typedef hive_uint hive_hier_id;
typedef hive_hier_id hive_device_id;
typedef hive_device_id hive_proc_id;
typedef hive_device_id hive_cell_id;
typedef hive_device_id hive_host_id;
typedef hive_device_id hive_bus_id;
typedef hive_device_id hive_bridge_id;
typedef hive_device_id hive_fifo_adapter_id;
typedef hive_device_id hive_custom_device_id;
typedef hive_uint hive_slot_id;
typedef hive_uint hive_fu_id;
typedef hive_uint hive_reg_file_id;
typedef hive_uint hive_reg_id;
/* Streaming devices */
typedef hive_uint hive_outport_id;
typedef hive_uint hive_inport_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
typedef char *hive_program;
typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IF_DEFS_H
#define _IF_DEFS_H
#define HIVE_IF_FRAME_REQUEST 0xA000
#define HIVE_IF_LINES_REQUEST 0xB000
#define HIVE_IF_VECTORS_REQUEST 0xC000
#endif /* _IF_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _if_subsystem_defs_h__
#define _if_subsystem_defs_h__
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10
#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0
/* order of the input bits for the ifmt irq controller */
#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0
#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1
#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2
#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3
#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3
/* order of the input bits for the ifmt Soft reset register */
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3
#endif /* _if_subsystem_defs_h__ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_selector_defs_h
#define _input_selector_defs_h
#ifndef HIVE_ISP_ISEL_SEL_BITS
#define HIVE_ISP_ISEL_SEL_BITS 2
#endif
#ifndef HIVE_ISP_CH_ID_BITS
#define HIVE_ISP_CH_ID_BITS 2
#endif
#ifndef HIVE_ISP_FMT_TYPE_BITS
#define HIVE_ISP_FMT_TYPE_BITS 5
#endif
/* gp_register register id's -- Outputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
#define HIVE_ISEL_GP_REGS_SOF_IDX 8
#define HIVE_ISEL_GP_REGS_EOF_IDX 9
#define HIVE_ISEL_GP_REGS_SOL_IDX 10
#define HIVE_ISEL_GP_REGS_EOL_IDX 11
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31
#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32
#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33
#define HIVE_ISEL_GP_REGS_SRST_IDX 37
#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0
#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1
#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2
#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3
/* gp_register register id's -- Inputs */
#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34
#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35
#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36
/* irq sources isel irq controller */
#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0
#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1
#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2
#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3
#define HIVE_ISEL_IRQ_NUM_IRQS 4
#endif /* _input_selector_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3
#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4
#endif /* _input_switch_2400_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_system_defs_h
#define _input_system_defs_h
/* csi controller modes */
#define HIVE_CSI_CONFIG_MAIN 0
#define HIVE_CSI_CONFIG_STEREO1 4
#define HIVE_CSI_CONFIG_STEREO2 8
/* general purpose register IDs */
/* Stream Multicast select modes */
#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0
#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1
#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2
/* Stream Mux select modes */
#define HIVE_ISYS_GPREG_MUX_IDX 3
/* streaming monitor status and control */
#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4
#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5
#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6
#define HIVE_ISYS_GPREG_SRST_IDX 7
#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8
#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9
#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10
/* Bit numbers of the soft reset register */
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1
#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2
#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3
#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4
#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5
#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6
#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7
#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8
#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9
/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13
#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14
/* -- */
#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15
#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16
#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17
#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv
#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22
#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23
#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1
#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3
#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4
#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5
/* streaming monitor port id's */
#define HIVE_ISYS_STR_MON_PORT_CAPA 0
#define HIVE_ISYS_STR_MON_PORT_CAPB 1
#define HIVE_ISYS_STR_MON_PORT_CAPC 2
#define HIVE_ISYS_STR_MON_PORT_ACQ 3
#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4
#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5
#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6
#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7
#define HIVE_ISYS_STR_MON_PORT_PIXA 8
#define HIVE_ISYS_STR_MON_PORT_PIXB 9
/* interrupt bit ID's */
#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0
#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1
#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2
#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4
#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5
#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6
#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7
/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/
#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8
#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9
/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/
#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10
#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11
/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/
#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12
/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/
#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13
#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14
#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15
#define HIVE_ISYS_IRQ_CIO2AHB 16
#define HIVE_ISYS_IRQ_DMA_BIT_ID 17
#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18
#define HIVE_ISYS_IRQ_NUM_BITS 19
/* DMA */
#define HIVE_ISYS_DMA_CHANNEL 0
#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0
#define HIVE_ISYS_DMA_HEIGHT 1
#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */
#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */
#define HIVE_ISYS_DMA_CROP 0 /* no cropping */
#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */
#endif /* _input_system_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _irq_controller_defs_h
#define _irq_controller_defs_h
#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0
#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1
#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2
#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3
#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4
#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5
#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
#endif /* _irq_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _isp2400_support_h
#define _isp2400_support_h
#ifndef ISP2400_VECTOR_TYPES
/* This typedef is to be able to include hive header files
in the host code which is useful in crun */
typedef char *tmemvectors, *tmemvectoru, *tvector;
#endif
#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val)
#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val)
#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem)
#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem)
#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell))
#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell))
#if ISP_HAS_HIST
#define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram)
#define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell))
#endif
#endif /* _isp2400_support_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _mmu_defs_h
#define _mmu_defs_h
#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0
#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1
#define _HRT_MMU_REG_ALIGN 4
#endif /* _mmu_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _scalar_processor_2400_params_h
#define _scalar_processor_2400_params_h
#include "cell_params.h"
#endif /* _scalar_processor_2400_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _ST2MEM_DEFS_H
#define _ST2MEM_DEFS_H
#define _STR2MEM_CRUN_BIT 0x100000
#define _STR2MEM_CMD_BITS 0x0F0000
#define _STR2MEM_COUNT_BITS 0x00FFFF
#define _STR2MEM_BLOCKS_CMD 0xA0000
#define _STR2MEM_PACKETS_CMD 0xB0000
#define _STR2MEM_BYTES_CMD 0xC0000
#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
#define _STR2MEM_SOFT_RESET_REG_ID 0
#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1
#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2
#define _STR2MEM_BIT_SWAPPING_REG_ID 3
#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4
#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5
#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6
#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7
#define _STR2MEM_EN_STAT_UPDATE_ID 8
#define _STR2MEM_REG_ALIGN 4
#endif /* _ST2MEM_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _streaming_to_mipi_defs_h
#define _streaming_to_mipi_defs_h
#define HIVE_STR_TO_MIPI_VALID_A_BIT 0
#define HIVE_STR_TO_MIPI_VALID_B_BIT 1
#define HIVE_STR_TO_MIPI_SOL_BIT 2
#define HIVE_STR_TO_MIPI_EOL_BIT 3
#define HIVE_STR_TO_MIPI_SOF_BIT 4
#define HIVE_STR_TO_MIPI_EOF_BIT 5
#define HIVE_STR_TO_MIPI_CH_ID_LSB 6
#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1)
#endif /* _streaming_to_mipi_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _timed_controller_defs_h
#define _timed_controller_defs_h
#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
#endif /* _timed_controller_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_VERSION_H
#define HRT_VERSION_H
#define HRT_VERSION_MAJOR 1
#define HRT_VERSION_MINOR 4
#define HRT_VERSION 1_4
#endif
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifdef IA_CSS_INCLUDE_CONFIGURATIONS
#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h"
#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h"
#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h"
#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h"
#include "isp/kernels/output/output_1.0/ia_css_output.host.h"
#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h"
#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h"
/* ISP2401 */
#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h"
#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h"
#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h"
#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_CONFIG_H
#define _IA_CSS_ISP_CONFIG_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_configuration_ids {
IA_CSS_ITERATOR_CONFIG_ID,
IA_CSS_COPY_OUTPUT_CONFIG_ID,
IA_CSS_CROP_CONFIG_ID,
IA_CSS_FPN_CONFIG_ID,
IA_CSS_DVS_CONFIG_ID,
IA_CSS_QPLANE_CONFIG_ID,
IA_CSS_OUTPUT0_CONFIG_ID,
IA_CSS_OUTPUT1_CONFIG_ID,
IA_CSS_OUTPUT_CONFIG_ID,
IA_CSS_RAW_CONFIG_ID,
IA_CSS_TNR_CONFIG_ID,
IA_CSS_REF_CONFIG_ID,
IA_CSS_VF_CONFIG_ID,
/* ISP2401 */
IA_CSS_SC_CONFIG_ID,
IA_CSS_NUM_CONFIGURATION_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_config_memory_offsets {
struct {
struct ia_css_isp_parameter iterator;
struct ia_css_isp_parameter copy_output;
struct ia_css_isp_parameter crop;
struct ia_css_isp_parameter fpn;
struct ia_css_isp_parameter dvs;
struct ia_css_isp_parameter qplane;
struct ia_css_isp_parameter output0;
struct ia_css_isp_parameter output1;
struct ia_css_isp_parameter output;
#ifdef ISP2401
struct ia_css_isp_parameter sc;
#endif
struct ia_css_isp_parameter raw;
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
struct ia_css_isp_parameter vf;
} dmem;
};
#if defined(IA_CSS_INCLUDE_CONFIGURATIONS)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_iterator(
const struct ia_css_binary *binary,
const struct ia_css_iterator_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_copy_output(
const struct ia_css_binary *binary,
const struct ia_css_copy_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_crop(
const struct ia_css_binary *binary,
const struct ia_css_crop_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_fpn(
const struct ia_css_binary *binary,
const struct ia_css_fpn_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_dvs(
const struct ia_css_binary *binary,
const struct ia_css_dvs_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_qplane(
const struct ia_css_binary *binary,
const struct ia_css_qplane_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output0(
const struct ia_css_binary *binary,
const struct ia_css_output0_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output1(
const struct ia_css_binary *binary,
const struct ia_css_output1_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_output(
const struct ia_css_binary *binary,
const struct ia_css_output_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
/* ISP2401 */
void
ia_css_configure_sc(
const struct ia_css_binary *binary,
const struct ia_css_sc_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_raw(
const struct ia_css_binary *binary,
const struct ia_css_raw_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_tnr(
const struct ia_css_binary *binary,
const struct ia_css_tnr_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_ref(
const struct ia_css_binary *binary,
const struct ia_css_ref_configuration *config_dmem);
/* Code generated by genparam/genconfig.c:gen_configure_function() */
void
ia_css_configure_vf(
const struct ia_css_binary *binary,
const struct ia_css_vf_configuration *config_dmem);
#endif /* IA_CSS_INCLUDE_CONFIGURATION */
#endif /* _IA_CSS_ISP_CONFIG_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#define IA_CSS_INCLUDE_STATES
#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h"
#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h"
#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h"
#include "isp/kernels/de/de_1.0/ia_css_de.host.h"
#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h"
#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h"
#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h"
#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h"
#include "isp/kernels/dpc2/ia_css_dpc2.host.h"
#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h"
/* Generated code: do not edit or commmit. */
#ifndef _IA_CSS_ISP_STATE_H
#define _IA_CSS_ISP_STATE_H
/* Code generated by genparam/gencode.c:gen_param_enum() */
enum ia_css_state_ids {
IA_CSS_AA_STATE_ID,
IA_CSS_CNR_STATE_ID,
IA_CSS_CNR2_STATE_ID,
IA_CSS_DP_STATE_ID,
IA_CSS_DE_STATE_ID,
IA_CSS_TNR_STATE_ID,
IA_CSS_REF_STATE_ID,
IA_CSS_YNR_STATE_ID,
IA_CSS_NUM_STATE_IDS
};
/* Code generated by genparam/gencode.c:gen_param_offsets() */
struct ia_css_state_memory_offsets {
struct {
struct ia_css_isp_parameter aa;
struct ia_css_isp_parameter cnr;
struct ia_css_isp_parameter cnr2;
struct ia_css_isp_parameter dp;
struct ia_css_isp_parameter de;
struct ia_css_isp_parameter ynr;
} vmem;
struct {
struct ia_css_isp_parameter tnr;
struct ia_css_isp_parameter ref;
} dmem;
};
#if defined(IA_CSS_INCLUDE_STATES)
#include "ia_css_stream.h" /* struct ia_css_stream */
#include "ia_css_binary.h" /* struct ia_css_binary */
/* Code generated by genparam/genstate.c:gen_state_init_table() */
extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(
const struct ia_css_binary *binary);
#endif /* IA_CSS_INCLUDE_STATE */
#endif /* _IA_CSS_ISP_STATE_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/bits.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_BITS_H
#define _HRT_BITS_H
#include "defs.h"
#define _hrt_ones(n) HRTCAT(_hrt_ones_, n)
#define _hrt_ones_0x0 0x00000000U
#define _hrt_ones_0x1 0x00000001U
#define _hrt_ones_0x2 0x00000003U
#define _hrt_ones_0x3 0x00000007U
#define _hrt_ones_0x4 0x0000000FU
#define _hrt_ones_0x5 0x0000001FU
#define _hrt_ones_0x6 0x0000003FU
#define _hrt_ones_0x7 0x0000007FU
#define _hrt_ones_0x8 0x000000FFU
#define _hrt_ones_0x9 0x000001FFU
#define _hrt_ones_0xA 0x000003FFU
#define _hrt_ones_0xB 0x000007FFU
#define _hrt_ones_0xC 0x00000FFFU
#define _hrt_ones_0xD 0x00001FFFU
#define _hrt_ones_0xE 0x00003FFFU
#define _hrt_ones_0xF 0x00007FFFU
#define _hrt_ones_0x10 0x0000FFFFU
#define _hrt_ones_0x11 0x0001FFFFU
#define _hrt_ones_0x12 0x0003FFFFU
#define _hrt_ones_0x13 0x0007FFFFU
#define _hrt_ones_0x14 0x000FFFFFU
#define _hrt_ones_0x15 0x001FFFFFU
#define _hrt_ones_0x16 0x003FFFFFU
#define _hrt_ones_0x17 0x007FFFFFU
#define _hrt_ones_0x18 0x00FFFFFFU
#define _hrt_ones_0x19 0x01FFFFFFU
#define _hrt_ones_0x1A 0x03FFFFFFU
#define _hrt_ones_0x1B 0x07FFFFFFU
#define _hrt_ones_0x1C 0x0FFFFFFFU
#define _hrt_ones_0x1D 0x1FFFFFFFU
#define _hrt_ones_0x1E 0x3FFFFFFFU
#define _hrt_ones_0x1F 0x7FFFFFFFU
#define _hrt_ones_0x20 0xFFFFFFFFU
#define _hrt_ones_0 _hrt_ones_0x0
#define _hrt_ones_1 _hrt_ones_0x1
#define _hrt_ones_2 _hrt_ones_0x2
#define _hrt_ones_3 _hrt_ones_0x3
#define _hrt_ones_4 _hrt_ones_0x4
#define _hrt_ones_5 _hrt_ones_0x5
#define _hrt_ones_6 _hrt_ones_0x6
#define _hrt_ones_7 _hrt_ones_0x7
#define _hrt_ones_8 _hrt_ones_0x8
#define _hrt_ones_9 _hrt_ones_0x9
#define _hrt_ones_10 _hrt_ones_0xA
#define _hrt_ones_11 _hrt_ones_0xB
#define _hrt_ones_12 _hrt_ones_0xC
#define _hrt_ones_13 _hrt_ones_0xD
#define _hrt_ones_14 _hrt_ones_0xE
#define _hrt_ones_15 _hrt_ones_0xF
#define _hrt_ones_16 _hrt_ones_0x10
#define _hrt_ones_17 _hrt_ones_0x11
#define _hrt_ones_18 _hrt_ones_0x12
#define _hrt_ones_19 _hrt_ones_0x13
#define _hrt_ones_20 _hrt_ones_0x14
#define _hrt_ones_21 _hrt_ones_0x15
#define _hrt_ones_22 _hrt_ones_0x16
#define _hrt_ones_23 _hrt_ones_0x17
#define _hrt_ones_24 _hrt_ones_0x18
#define _hrt_ones_25 _hrt_ones_0x19
#define _hrt_ones_26 _hrt_ones_0x1A
#define _hrt_ones_27 _hrt_ones_0x1B
#define _hrt_ones_28 _hrt_ones_0x1C
#define _hrt_ones_29 _hrt_ones_0x1D
#define _hrt_ones_30 _hrt_ones_0x1E
#define _hrt_ones_31 _hrt_ones_0x1F
#define _hrt_ones_32 _hrt_ones_0x20
#define _hrt_mask(b, n) \
(_hrt_ones(n) << (b))
#define _hrt_get_bits(w, b, n) \
(((w) >> (b)) & _hrt_ones(n))
#define _hrt_set_bits(w, b, n, v) \
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \
_hrt_set_bits(w, 16, 16, v)
#endif /* _HRT_BITS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/cell_params.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _cell_params_h
#define _cell_params_h
#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/
#define SP_ICACHE_TAG_BITS 4 /*size of tag*/
#define SP_ICACHE_SET_BITS 8 /* 256 sets*/
#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
#define SP_FIFO_2_DEPTH 0
#define SP_FIFO_3_DEPTH 0
#define SP_FIFO_4_DEPTH 0
#define SP_FIFO_5_DEPTH 0
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _HRT_DEFS_H_
#define _HRT_DEFS_H_
#ifndef HRTCAT
#define _HRTCAT(m, n) m##n
#define HRTCAT(m, n) _HRTCAT(m, n)
#endif
#ifndef HRTSTR
#define _HRTSTR(x) #x
#define HRTSTR(x) _HRTSTR(x)
#endif
#ifndef HRTMIN
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#endif /* _HRT_DEFS_H_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/dma_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _dma_v2_defs_h
#define _dma_v2_defs_h
#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels
#define _DMA_V2_CONNECTIONS_ID Connections
#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths
#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth
#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat
#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass
#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst
#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept
#define _DMA_V2_DEV_SRMD_ID DevSRMD
#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters
#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth
#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth
#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat
#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass
#define _DMA_V2_NO_PACK_ID has_no_pack
#define _DMA_V2_REG_ALIGN 4
#define _DMA_V2_REG_ADDR_BITS 2
/* Command word */
#define _DMA_V2_CMD_IDX 0
#define _DMA_V2_CMD_BITS 6
#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
#define _DMA_V2_CHANNEL_BITS 5
/* The command to set a parameter contains the PARAM field next */
#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_PARAM_BITS 4
/* Commands to read, write or init specific blocks contain these
three values */
#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_DEV_A_XB_BITS 8
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
#define _DMA_V2_CMD_CTRL_BITS 4
/* Packing setup word */
#define _DMA_V2_CONNECTION_IDX 0
#define _DMA_V2_CONNECTION_BITS 4
#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
#define _DMA_V2_EXTENSION_BITS 1
/* Elements packing word */
#define _DMA_V2_ELEMENTS_IDX 0
#define _DMA_V2_ELEMENTS_BITS 8
#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
#define _DMA_V2_LEFT_CROPPING_BITS 8
#define _DMA_V2_WIDTH_IDX 0
#define _DMA_V2_WIDTH_BITS 16
#define _DMA_V2_HEIGHT_IDX 0
#define _DMA_V2_HEIGHT_BITS 16
#define _DMA_V2_STRIDE_IDX 0
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
#define _DMA_V2_SIGN_EXTEND 1
/* SLAVE address map */
#define _DMA_V2_SEL_FSM_CMD 0
#define _DMA_V2_SEL_CH_REG 1
#define _DMA_V2_SEL_CONN_GROUP 2
#define _DMA_V2_SEL_DEV_INTERF 3
#define _DMA_V2_ADDR_SEL_COMP_IDX 12
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1
#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2
#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8
#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14
#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15
#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4
#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2
#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3
#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0
#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1
#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2
#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3
#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4
#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5
#endif /* _dma_v2_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef HRT_GDC_v2_defs_h_
#define HRT_GDC_v2_defs_h_
#define HRT_GDC_IS_V2
#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
#define HRT_GDC_REG_ID_POS 25
#define HRT_GDC_REG_ID_BITS 5
#define HRT_GDC_DATA_POS 0
#define HRT_GDC_DATA_BITS 25
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
#define HRT_GDC_PERF_1_1_pix 0
#define HRT_GDC_PERF_2_1_pix 1
#define HRT_GDC_PERF_1_2_pix 2
#define HRT_GDC_PERF_2_2_pix 3
#define HRT_GDC_NND_MODE 0
#define HRT_GDC_BLI_MODE 1
#define HRT_GDC_BCI_MODE 2
#define HRT_GDC_LUT_MODE 3
#define HRT_GDC_SCAN_STB 0
#define HRT_GDC_SCAN_STR 1
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
#define HRT_GDC_CE_OPY_LEN 14
#define HRT_GDC_CE_OPX_POS 16
#define HRT_GDC_CE_OPX_LEN 16
// CHK_ENGINE register bit-map:
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
#define HRT_GDC_BPP_IDX 3
#define HRT_GDC_FRYIPXFRX_IDX 4
#define HRT_GDC_OXDIM_IDX 5
#define HRT_GDC_OYDIM_IDX 6
#define HRT_GDC_SRC_ADDR_IDX 7
#define HRT_GDC_SRC_END_ADDR_IDX 8
#define HRT_GDC_SRC_WRAP_ADDR_IDX 9
#define HRT_GDC_SRC_STRIDE_IDX 10
#define HRT_GDC_DST_ADDR_IDX 11
#define HRT_GDC_DST_STRIDE_IDX 12
#define HRT_GDC_DX_IDX 13
#define HRT_GDC_DY_IDX 14
#define HRT_GDC_P0X_IDX 15
#define HRT_GDC_P0Y_IDX 16
#define HRT_GDC_P1X_IDX 17
#define HRT_GDC_P1Y_IDX 18
#define HRT_GDC_P2X_IDX 19
#define HRT_GDC_P2Y_IDX 20
#define HRT_GDC_P3X_IDX 21
#define HRT_GDC_P3Y_IDX 22
#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT
#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_timer_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gp_timer_defs_h
#define _gp_timer_defs_h
#define _HRT_GP_TIMER_REG_ALIGN 4
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gpio_block_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _gpio_block_defs_h_
#define _gpio_block_defs_h_
#define _HRT_GPIO_BLOCK_REG_ALIGN 4
/* R/W registers */
#define _gpio_block_reg_do_e 0
#define _gpio_block_reg_do_select 1
#define _gpio_block_reg_do_0 2
#define _gpio_block_reg_do_1 3
#define _gpio_block_reg_do_pwm_cnt_0 4
#define _gpio_block_reg_do_pwm_cnt_1 5
#define _gpio_block_reg_do_pwm_cnt_2 6
#define _gpio_block_reg_do_pwm_cnt_3 7
#define _gpio_block_reg_do_pwm_main_cnt 8
#define _gpio_block_reg_do_pwm_enable 9
#define _gpio_block_reg_di_debounce_sel 10
#define _gpio_block_reg_di_debounce_cnt_0 11
#define _gpio_block_reg_di_debounce_cnt_1 12
#define _gpio_block_reg_di_debounce_cnt_2 13
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16
#endif /* _gpio_block_defs_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_
#define _hive_isp_css_streaming_to_mipi_types_hrt_h_
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/if_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _IF_DEFS_H
#define _IF_DEFS_H
#define HIVE_IF_FRAME_REQUEST 0xA000
#define HIVE_IF_LINES_REQUEST 0xB000
#define HIVE_IF_VECTORS_REQUEST 0xC000
#endif /* _IF_DEFS_H */
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_switch_2400_defs.h deleted 100644 → 0
View file @ c8b1a84e
/*
* Support for Intel Camera Imaging ISP subsystem.
* Copyright (c) 2015, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3
#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1
#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2
#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4
#endif /* _input_switch_2400_defs_h */
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