Commit 7d740a06 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Paul Mundt

sh: Add support for SH7763 CPU subtype.

Signed-off-by: default avatarYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 0465b9fb
...@@ -265,6 +265,12 @@ config CPU_SUBTYPE_SH4_202 ...@@ -265,6 +265,12 @@ config CPU_SUBTYPE_SH4_202
# SH-4A Processor Support # SH-4A Processor Support
config CPU_SUBTYPE_SH7763
bool "Support SH7763 processor"
select CPU_SH4A
help
Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
config CPU_SUBTYPE_SH7770 config CPU_SUBTYPE_SH7770
bool "Support SH7770 processor" bool "Support SH7770 processor"
select CPU_SH4A select CPU_SH4A
...@@ -551,7 +557,8 @@ config SH_MTU2 ...@@ -551,7 +557,8 @@ config SH_MTU2
config SH_TIMER_IRQ config SH_TIMER_IRQ
int int
default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
CPU_SUBTYPE_SH7763
default "86" if CPU_SUBTYPE_SH7619 default "86" if CPU_SUBTYPE_SH7619
default "140" if CPU_SUBTYPE_SH7206 default "140" if CPU_SUBTYPE_SH7206
default "16" default "16"
......
...@@ -29,7 +29,7 @@ config EARLY_SCIF_CONSOLE ...@@ -29,7 +29,7 @@ config EARLY_SCIF_CONSOLE
config EARLY_SCIF_CONSOLE_PORT config EARLY_SCIF_CONSOLE_PORT
hex hex
depends on EARLY_SCIF_CONSOLE depends on EARLY_SCIF_CONSOLE
default "0xffe00000" if CPU_SUBTYPE_SH7780 default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
default "0xffea0000" if CPU_SUBTYPE_SH7785 default "0xffea0000" if CPU_SUBTYPE_SH7785
default "0xfffe8000" if CPU_SUBTYPE_SH7203 default "0xfffe8000" if CPU_SUBTYPE_SH7203
default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
......
...@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o ...@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
......
#ifndef __PCI_SH4_H #ifndef __PCI_SH4_H
#define __PCI_SH4_H #define __PCI_SH4_H
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
defined(CONFIG_CPU_SUBTYPE_SH7763)
#include "pci-sh7780.h" #include "pci-sh7780.h"
#else #else
#include "pci-sh7751.h" #include "pci-sh7751.h"
......
...@@ -58,6 +58,7 @@ static int __init sh7780_pci_init(void) ...@@ -58,6 +58,7 @@ static int __init sh7780_pci_init(void)
id = pci_read_reg(SH7780_PCIVID); id = pci_read_reg(SH7780_PCIVID);
if ((id & 0xffff) == SH7780_VENDOR_ID) { if ((id & 0xffff) == SH7780_VENDOR_ID) {
switch ((id >> 16) & 0xffff) { switch ((id >> 16) & 0xffff) {
case SH7763_DEVICE_ID:
case SH7780_DEVICE_ID: case SH7780_DEVICE_ID:
case SH7781_DEVICE_ID: case SH7781_DEVICE_ID:
case SH7785_DEVICE_ID: case SH7785_DEVICE_ID:
......
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#define SH7780_VENDOR_ID 0x1912 #define SH7780_VENDOR_ID 0x1912
#define SH7781_DEVICE_ID 0x0001 #define SH7781_DEVICE_ID 0x0001
#define SH7780_DEVICE_ID 0x0002 #define SH7780_DEVICE_ID 0x0002
#define SH7763_DEVICE_ID 0x0004
#define SH7785_DEVICE_ID 0x0007 #define SH7785_DEVICE_ID 0x0007
/* SH7780 Control Registers */ /* SH7780 Control Registers */
......
...@@ -98,6 +98,8 @@ int __init detect_cpu_and_cache_system(void) ...@@ -98,6 +98,8 @@ int __init detect_cpu_and_cache_system(void)
case 0x200A: case 0x200A:
if (prr == 0x61) if (prr == 0x61)
boot_cpu_data.type = CPU_SH7781; boot_cpu_data.type = CPU_SH7781;
else if (prr == 0xa1)
boot_cpu_data.type = CPU_SH7763;
else else
boot_cpu_data.type = CPU_SH7780; boot_cpu_data.type = CPU_SH7780;
......
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
# #
# CPU subtype setup # CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
...@@ -14,6 +15,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o ...@@ -14,6 +15,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o
# Primary on-chip clocks (common) # Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
......
/*
* arch/sh/kernel/cpu/sh4a/clock-sh7763.c
*
* SH7763 support for the clock framework
*
* Copyright (C) 2005 Paul Mundt
* Copyright (C) 2007 Yoshihiro Shimoda
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>
static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 };
static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
static void master_clk_init(struct clk *clk)
{
clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
}
static struct clk_ops sh7763_master_clk_ops = {
.init = master_clk_init,
};
static void module_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
clk->rate = clk->parent->rate / p0fc_divisors[idx];
}
static struct clk_ops sh7763_module_clk_ops = {
.recalc = module_clk_recalc,
};
static void bus_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
clk->rate = clk->parent->rate / bfc_divisors[idx];
}
static struct clk_ops sh7763_bus_clk_ops = {
.recalc = bus_clk_recalc,
};
static void cpu_clk_recalc(struct clk *clk)
{
clk->rate = clk->parent->rate;
}
static struct clk_ops sh7763_cpu_clk_ops = {
.recalc = cpu_clk_recalc,
};
static struct clk_ops *sh7763_clk_ops[] = {
&sh7763_master_clk_ops,
&sh7763_module_clk_ops,
&sh7763_bus_clk_ops,
&sh7763_cpu_clk_ops,
};
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
if (idx < ARRAY_SIZE(sh7763_clk_ops))
*ops = sh7763_clk_ops[idx];
}
static void shyway_clk_recalc(struct clk *clk)
{
int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
clk->rate = clk->parent->rate / cfc_divisors[idx];
}
static struct clk_ops sh7763_shyway_clk_ops = {
.recalc = shyway_clk_recalc,
};
static struct clk sh7763_shyway_clk = {
.name = "shyway_clk",
.flags = CLK_ALWAYS_ENABLED,
.ops = &sh7763_shyway_clk_ops,
};
/*
* Additional SH7763-specific on-chip clocks that aren't already part of the
* clock framework
*/
static struct clk *sh7763_onchip_clocks[] = {
&sh7763_shyway_clk,
};
static int __init sh7763_clk_init(void)
{
struct clk *clk = clk_get(NULL, "master_clk");
int i;
for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
struct clk *clkp = sh7763_onchip_clocks[i];
clkp->parent = clk;
clk_register(clkp);
clk_enable(clkp);
}
/*
* Now that we have the rest of the clocks registered, we need to
* force the parent clock to propagate so that these clocks will
* automatically figure out their rate. We cheat by handing the
* parent clock its current rate and forcing child propagation.
*/
clk_set_rate(clk, clk_get_rate(clk));
clk_put(clk);
return 0;
}
arch_initcall(sh7763_clk_init);
This diff is collapsed.
...@@ -319,10 +319,10 @@ static const char *cpu_name[] = { ...@@ -319,10 +319,10 @@ static const char *cpu_name[] = {
[CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751", [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
[CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760", [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501", [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
[CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722", [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
[CPU_SHX3] = "SH-X3", [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
[CPU_SH_NONE] = "Unknown" [CPU_SH_NONE] = "Unknown"
}; };
......
...@@ -395,7 +395,8 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) ...@@ -395,7 +395,8 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
} else { } else {
#ifdef CONFIG_CPU_SUBTYPE_SH7343 #ifdef CONFIG_CPU_SUBTYPE_SH7343
/* Nothing */ /* Nothing */
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \ #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) || \
defined(CONFIG_CPU_SUBTYPE_SHX3) defined(CONFIG_CPU_SUBTYPE_SHX3)
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
...@@ -408,6 +409,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) ...@@ -408,6 +409,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
#endif #endif
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) defined(CONFIG_CPU_SUBTYPE_SH7785)
static inline int scif_txroom(struct uart_port *port) static inline int scif_txroom(struct uart_port *port)
......
...@@ -120,6 +120,12 @@ ...@@ -120,6 +120,12 @@
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCI_ONLY # define SCI_ONLY
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH7770) #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
# define SCSPTR0 0xff923020 /* 16 bit SCIF */ # define SCSPTR0 0xff923020 /* 16 bit SCIF */
# define SCSPTR1 0xff924020 /* 16 bit SCIF */ # define SCSPTR1 0xff924020 /* 16 bit SCIF */
...@@ -419,6 +425,7 @@ SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) ...@@ -419,6 +425,7 @@ SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) defined(CONFIG_CPU_SUBTYPE_SH7785)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
...@@ -588,6 +595,15 @@ static inline int sci_rxd_in(struct uart_port *port) ...@@ -588,6 +595,15 @@ static inline int sci_rxd_in(struct uart_port *port)
int ch = (port->mapbase - SMR0) >> 3; int ch = (port->mapbase - SMR0) >> 3;
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
} }
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe08000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7770) #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
static inline int sci_rxd_in(struct uart_port *port) static inline int sci_rxd_in(struct uart_port *port)
{ {
...@@ -698,7 +714,8 @@ static inline int sci_rxd_in(struct uart_port *port) ...@@ -698,7 +714,8 @@ static inline int sci_rxd_in(struct uart_port *port)
* -- Mitch Davis - 15 Jul 2000 * -- Mitch Davis - 15 Jul 2000
*/ */
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785) defined(CONFIG_CPU_SUBTYPE_SH7785)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
......
...@@ -35,7 +35,7 @@ static void __init check_bugs(void) ...@@ -35,7 +35,7 @@ static void __init check_bugs(void)
case CPU_SH7750 ... CPU_SH4_501: case CPU_SH7750 ... CPU_SH4_501:
*p++ = '4'; *p++ = '4';
break; break;
case CPU_SH7770 ... CPU_SHX3: case CPU_SH7763 ... CPU_SHX3:
*p++ = '4'; *p++ = '4';
*p++ = 'a'; *p++ = 'a';
break; break;
......
...@@ -16,7 +16,8 @@ ...@@ -16,7 +16,8 @@
#define SCLKACR 0xa4150008 #define SCLKACR 0xa4150008
#define SCLKBCR 0xa415000c #define SCLKBCR 0xa415000c
#define IrDACLKCR 0xa4150010 #define IrDACLKCR 0xa4150010
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
#define FRQCR 0xffc80000 #define FRQCR 0xffc80000
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
#define FRQCR0 0xffc80000 #define FRQCR0 0xffc80000
......
...@@ -30,7 +30,7 @@ enum cpu_type { ...@@ -30,7 +30,7 @@ enum cpu_type {
CPU_SH7760, CPU_SH4_202, CPU_SH4_501, CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */ /* SH-4A types */
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
/* SH4AL-DSP types */ /* SH4AL-DSP types */
CPU_SH7343, CPU_SH7722, CPU_SH7343, CPU_SH7722,
......
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