arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a
plus ECBHB which was RES0 in DDI0487H.a but has been subsequently
defined and is already present in mainline. No functional changes.
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-23-broonie@kernel.orgSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm64/include/asm/sysreg.h

@@ -199,7 +199,6 @@
 #define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
 #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
 
-#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
@@ -750,28 +749,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-/* id_aa64mmfr1 */
-#define ID_AA64MMFR1_EL1_ECBHB_SHIFT		60
-#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT		52
-#define ID_AA64MMFR1_EL1_HCX_SHIFT		40
-#define ID_AA64MMFR1_EL1_AFP_SHIFT		44
-#define ID_AA64MMFR1_EL1_ETS_SHIFT		36
-#define ID_AA64MMFR1_EL1_TWED_SHIFT		32
-#define ID_AA64MMFR1_EL1_XNX_SHIFT		28
-#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT		24
-#define ID_AA64MMFR1_EL1_PAN_SHIFT		20
-#define ID_AA64MMFR1_EL1_LO_SHIFT		16
-#define ID_AA64MMFR1_EL1_HPDS_SHIFT		12
-#define ID_AA64MMFR1_EL1_VH_SHIFT		8
-#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT		4
-#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT		0
-
-#define ID_AA64MMFR1_EL1_VMIDBits_8		0
-#define ID_AA64MMFR1_EL1_VMIDBits_16		2
-
-#define ID_AA64MMFR1_EL1_TIDCP1_NI		0
-#define ID_AA64MMFR1_EL1_TIDCP1_IMP		1
-
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_EL1_E0PD_SHIFT	60
 #define ID_AA64MMFR2_EL1_EVT_SHIFT	56

arch/arm64/tools/sysreg

@@ -388,6 +388,77 @@ Enum	3:0	PARANGE
 EndEnum
 EndSysreg
 
+Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
+Enum	63:60	ECBHB
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	59:56	CMOW
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	TIDCP1
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	51:48	nTLBPA
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	47:44	AFP
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	HCX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	39:36	ETS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	TWED
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	XNX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	27:24	SpecSEI
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	PAN
+	0b0000	NI
+	0b0001	IMP
+	0b0010	PAN2
+	0b0011	PAN3
+EndEnum
+Enum	19:16	LO
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	HPDS
+	0b0000	NI
+	0b0001	IMP
+	0b0010	HPDS2
+EndEnum
+Enum	11:8	VH
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	7:4	VMIDBits
+	0b0000	8
+	0b0010	16
+EndEnum
+Enum	3:0	HAFDBS
+	0b0000	NI
+	0b0001	AF
+	0b0010	DBM
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINMASK